一种改进的VLSI电路有效布局算法

采用重心矩形约束[1]进行VLSI布局会出现以下问题：(1)布局边界的浪费,出现不可利用的小区域;(2)放置模块时可能会出现模块放置在实际有效区域内却因为重心约束成为非法放置。为了解决该问题,本文提出了一种改进文献[1]的VLSI布局启发式算法：通过设计模块的优先顺序进行合理布局,并辅助于边界矩形来解决重心矩形约束出现的问题;对模块布局放置的多个可能位置进行比较,并将其放置在优先度最高的适当区域。用Banchmark（ami33,ami49）和文献[1]的数据进行测试,结果表明新算法：（1）算法简洁高效,运行时间短;（2）布局结果明显好于文献[1]。     

基于Single-Sequence布图规划边界约束问题的研究

布图规划是VLSI设计中非常重要的步骤.在计算机辅助设计中,布图被表示成编码以使其容易被计算机处理.Single-Sequence就是一种非常有用的表示布图的编码方法.一个布图中,一些模块如输入输出模块,必须放置在芯片的边界处,这种限制被称为边界约束.本论文提出了用模拟退火算法寻求最优布圈的方法,有效地解决了布图规划的边界约束问题.     

求解单位等边三角形Packing问题的近似算法

多边形Packing问题不仅具有重要的理论意义，而且也有广阔的应用前景，由于该问题具有NP难度，且具有连续的性质，一般要事先对多边形的放置方位进行限制，例如不允许多边形旋转，然后再进行优化求得近似解，该文采用一种新的思路对多边形Packing问题的一个特例－单位等边三角形Packing问题进行了研究，提出了零自由度动作和零自由度放置策略的概念，并设计了一个近似求解算法－最小损伤法，复杂性分析和计算结果表明该算法是高效的，以此为基础，可能为多边形Packing问题找到类似的求解算法。     

基于拟人策略的带有预放置模块的布局算法

在超大规模集成电路设计中，一些特别重要的模块，像RAM、ROM和CPU等经常被优先放置，而其它模块则被两两互不重叠地放置在芯片的剩余区域。此类问题能被形式化为带有预放置模块的布局问题，关于此问题的求解方法多为随机优化方法。该文基于拟人的思想，提出了占角和最大穴度优先的放置策略，为该问题的快速求解提供了一种高效的启发式确定性算法。算法的高效性通过应用于标准电路MCNC得到了验证。     

An iterative merging algorithm for soft rectangle packing and its extension for application of fixed-outline floorplanning of soft modules

We address an important variant of the rectangle packing problem, the soft rectangle packing problem, and explore its problem extension for the fixed-outline floorplanning with soft modules. For the soft rectangle packing problem with zero deadspace, we present an iterative merging packing algorithm that merges all the rectangles into a final composite rectangle in a bottom-up order by iteratively merging two rectangles with the least areas into a composite rectangle, and then shapes and places each pair of sibling rectangles based on the dimensions and position of their composite rectangle in an up-bottom order. We prove that the proposed algorithm can guarantee feasible layout under some conditions, which are weaker as compared with a well-known zero-dead-space packing algorithm. We then provide a deadspace distribution strategy, which can systematically assign deadspace to modules, to extend the iterative merging packing algorithm to deal with soft packing problem with deadspace. For the fixed-outline floorplanning with soft modules problem, we propose an iterative merging packing based hierarchical partitioning algorithm, which adopts a general hierarchical partitioning framework as proposed in the popular PATOMA floorplanner. The framework uses a recursive bipartitioning method to partition the original problem into a set of subproblems, where each subproblem is a soft rectangle packing problem and how to solve the subproblem plays a key role in the final efficiency of the floorplanner. Different from the PATOMA that adopts the zero-dead-space packing algorithm, we adopt our proposed iterative merging packing algorithm for the subproblems. Experiments on the IBM-HB benchmarks show that the proposed packing algorithm is more effective than the zero-dead-space packing algorithm, and experiments on the GSRC benchmarks show that our floorplanning algorithm outperforms three state-of-the-art floorplanners PATOMA, DeFer and UFO, reducing wirelength by 0.2%, 4.0% and 2.3%, respectively.     

集成电路模块布局问题的一种有效算法

该文提出了一种求解集成电路模块布局问题的启发式算法。该算法通过设计一种合理的布局优先序,对同一模块可能的多个布局位置进行了比较,并将其放置在优先度最高的适当区域。实验结果表明,这一算法尽管简单,但对求解集成电路模块布局问题是有效的。     

New heuristics for one-dimensional bin-packing

Several new heuristics for solving the one-dimensional bin packing problem are presented. Some of these are based on the minimal bin slack (MBS) heuristic of Gupta and Ho. A different algorithm is one based on the variable neighbourhood search metaheuristic. The most effective algorithm turned out to be one based on running one of the former to provide an initial solution for the latter. When tested on 1370 benchmark test problem instances from two sources, this last hybrid algorithm proved capable of achieving the optimal solution for 1329, and could find for 4 instances solutions better than the best known. This is remarkable performance when set against other methods, both heuristic and optimum seeking.Scope and purposePacking items into boxes or bins is a task that occurs frequently in distribution and production. A large variety of different packing problems can be distinguished, depending on the size and shape of the items, as well as on the form and capacity of the bins (H. Dyckhoff and U. Finke, Cutting and Packing in Production and Distribution: a Typology and Bibliography, Springer, Berlin, 1992). Similar problems occur in minimising material wastage while cutting pieces into particular smaller ones and in the scheduling of identical processors in order to minimise total completion time. This work addresses the basic packing problem, known as the one-dimensional bin packing problem, where it is required to pack a number of items into the smallest possible number of bins of pre-specified equal capacity. Even though this problem is simple to state, it is NP hard, i.e., it is unlikely that there exists an algorithm that could solve every instance of it in polynomial time. Solution of more general realistic packing problems is probably contingent upon the availability of effective and computationally efficient solution procedures for the basic problem. In this work we present several heuristics capable of doing that. Extensive computational testing attests to the power of these heuristics, as well as to their computational efficiency.     

A parallel algorithm for tiling problems

A parallel algorithm for tiling with polyominoes is presented. The tiling problem is to pack polyominoes in a finite checkerboard. The algorithm using lxmxn processing elements requires O(1) time, where l is the number of different kinds of polyominoes on an mxn checkerboard. The algorithm can be used for placement of components or cells in a very large-scale integrated circuit (VLSI) chip, designing and compacting printed circuit boards, and solving a variety of two- or three-dimensional packing problems.     

一种改进的集成电路模块有效布局算法

改进了一种求解集成电路模块布局问题的启发式算法。以边界矩形周长最小为目标,设计了模块的优先序列,并在布局过程中动态调整,重新设计布局优先度,并简化模块的占边动作,重写占角动作,对模块布局放置的多个可能位置进行比较,并将其放置在优先度最高的适当区域。经实例测试,结果表明该算法简洁高效,面积利用率有较大提高。     

基于角模块链的不确定模块布图规划算法

布图规划是VLSI/SoC设计的重要步骤之一。为了缩短设计周期,在设计阶段的早期,也就是在模块物理信息没有完全确定之前就要进行布图规划,从而能估计出所设计的芯片的有关性能。因此,就必须开展不确定模块的布图规划研究。提出了一种基于角模块链(CornerBlockList,CBL)的不确定模块布图规划算法,采用模拟退火算法进行优化。实验结果表明,对于系统中有30%的模块信息不确定时,所获得的面积方差在1%左右,该算法是有效的。     

互连驱动的基于最小自由度优先原则的布局算法

在超大规模集成电路的布局问题中，布局模块间的互连特性变得日益重要。基于最小自由度优先的算法是一种有效的确定性布局算法，能够快速有效地解决布局问题。修改了原算法中局部互连的自由度，使用了更精确的模型，提出了一种全局互连的自由度，防止布局结果落入极小值区域，进一步改善了互连特性。实验结果证明，该方法在得到较好面积利用率的同时改善了互连的效果。     

Floorplan design of VLSI circuits

In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems.This work was partially supported by the Semiconductor Research Corporation under Contract 86-12-109, by the National Science Foundation under Grant MIP 8703273, and by a grant from the General Electric Company.     

An algorithm for the strip packing problem using collision free region and exact fitting placement

The irregular shape packing problem is approached. The container has a fixed width and an open dimension to be minimized. The proposed algorithm constructively creates the solution using an ordered list of items and a placement heuristic. Simulated annealing is the adopted metaheuristic to solve the optimization problem. A two-level algorithm is used to minimize the open dimension of the container. To ensure feasible layouts, the concept of collision free region is used. A collision free region represents all possible translations for an item to be placed and may be degenerated. For a moving item, the proposed placement heuristic detects the presence of exact fits (when the item is fully constrained by its surroundings) and exact slides (when the item position is constrained in all but one direction). The relevance of these positions is analyzed and a new placement heuristic is proposed. Computational comparisons on benchmark problems show that the proposed algorithm generated highly competitive solutions. Moreover, our algorithm updated some best known results.     

用角轮廓结构实现基于O-Tree表示法的模块快速放置算法

在VLSI物理设计中,O-Tree是一种高效简洁的布局表示法,但其对应的模块放置算法因为基于水平和垂直约束图及其操作而复杂且费时(算法时间复杂度为O(n2)).文中算法利用模块放置过程中右上端边沿形成的角轮廓结构的阶梯下降性,结合O-Tree编码结点间的父子关系,快速确定模块的放置位置.在模块的放置过程中不需要约束图,只保持一个角轮廓,使模块的放置更加简单高效,算法时间复杂度降低为O(nlogn). 在MCNC Benchmark上的实验结果验证了该算法的有效性.     

二维矩形条带装箱问题的底部左齐择优匹配算法

针对二维矩形条带装箱问题提出了一种启发式布局算法,即底部左齐择优匹配算法(lowest-level left align best fit,简称LLABF). LLABF算法遵循最佳匹配优先原则,该原则综合考虑完全匹配优先、宽度匹配优先、高度匹配优先、组合宽度匹配优先及可装入优先等启发式规则.与BL(bottom-left),IBL(improved-bottom-left)与BLF(bottom-left-fill)等启发算法不同的是,LLABF能够在矩形装入过程中自动选择与可装区域匹配的下一个待装矩形     

一种含浮动端点的斯坦纳树的构造算法

在集成电路的自动布图技术中，在完成布局过程，即各模块（或子电路单元）的拓扑位置确定以后，布线需要完成各电路模块之间的连接。斯坦纳树的构造问题可以应用于总体布线；如果考虑已有单元或连线的障碍，它也可以应用于详细布线。     

Evolutionary Algorithms for Minimax Problems in Robust Design

Many robust design problems can be described by minimax optimization problems. Classical techniques for solving these problems have typically been limited to a discrete form of the problem. More recently, evolutionary algorithms, particularly coevolutionary optimization techniques, have been applied to minimax problems. A new method of solving minimax optimization problems using evolutionary algorithms is proposed. The performance of this algorithm is shown to compare favorably with the existing methods on test problems. The performance of the algorithm is demonstrated on a robust pole placement problem and a ship engineering plant design problem.     

利用改进的差分进化算法求解等圆Packing问题

等圆Packing问题属于强约束的复杂组合优化问题之一,针对其强约束特点及难点,通过改进传统的差分进化算法,提出一种等圆Packing问题的求解方法。该改进算法特点是将有效解空间加入差分进化的变异约束中,并采用随机排序机制改进差分进化的选择机制。通过多次实验,表明此算法在求解小规模等圆Packing问题上取得的效果与目前所能找到的最优值相差不到0.6%,从而验证了演化计算在求解等圆Packing问题的可行性;与此同时,演化算法具有很好的收敛性,因此在其他强约束的复杂优化问题上将有很好的应用。     

基于GA-SA混合算法的VLSI门阵列布局设计

布局是VLSI布图设计中的关键环节，通常采用随机优化算法。该文采用遗传算法(GA)与模拟退火法(SA)相结合的搜索算法实现VLSI门阵列模式布局，利用遗传算法进行全局搜索，模拟退火法进行局部搜索。进化过程中采用精英保留策略，并对进化结果进行有选择的模拟退火操作，这样既加强了局部搜索能力又防止陷入局部最优。在复合布局目标函数中引入对最长线网的惩罚，其收敛速度比以总线长度为单一目标函数的要快。在交叉操作中，对交叉位置的选择采用了一种新的策略，增加了交叉的有效性。实验表明，此算法与简单遗传算法相比，有效地提高了全局搜索能力。     

求解不等圆Packing问题的一个启发式算法

求解具有NP难度的圆形packing问题具有很高的理论与实用价值.现提出一个启发式方法,求解了货运中常遇到的矩形区域内的不等圆packing问题.此算法首先将待布局圆按半径大小降序排列,然后用占角动作来逐个放置.通过试探性地放入一个或多个待布局圆,给出了占角动作的度以及更全局的有限枚举策略来评价占角动作的优度.在放置每一个圆时,以贪心的方式选取当前具有最大优度的占角动作来放置.最后用测试算例验证了算法的高效性.