A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI

A 200-MHz 16-b BiCMOS super high-speed signal processing (SSSP) circuit has been developed for high-speed digital signal processor (DSP) LSIs. In order to produce extremely fast LSI circuits, several novel techniques have been combined for integration of the SSSP. They include a redundant binary convolver architecture, a double-stage pipelined convolver architecture, and submicrometer BiCMOS drivers with large capacitive load drivability. The SSSP performs 200-MHz addition. The chip, which was fabricated with 0.8-μm BiCMOS and triple-layer metallization technology, has an area of 5.87 mm×5.74 mm and contains 20150 transistors. It operates at a clock frequency of 200 MHz with a single 5-V power supply and typically consumes 800 mW     

A 1.4-V 25-Mw 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30. 1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm~2 in the 0.13-μm CMOS process.     

A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter(ADC) is presented.This ADC with single track-and-hold(T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers.The prototype ADC achieves 5.55 bits of the effective number of bits(ENOB) and 47.84 dB of the spurious free dynamic range(SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate;it achieves 5.48 bit of ENOB a...     

New radio paging system and its propagation characteristics

A radio paging system using a 200 band NRZ-digital code for the selective calling signal on new frequency bands is discussed. This system uses the 250-MHz band, and its propagation characteristics in urban areas, necessary for the radio system design, was measured in the Tokyo area. Distance versus median field strength characteristics in this band approximate that of the 150-MHz band. Building loss is 19.7 dB and is less than that of the 150-MHz band. Therefore, the new system will provide nearly the same grade of service as the former system using the 150-MHz band.     

An 18-μA standby current 1.8-V, 200-MHz microprocessor withself-substrate-biased data-retention mode

A low-standby-current 1.8-V, 200-MHz microprocessor has been fabricated with a 0.2-μm, five-metal, dual-oxide-thickness, CMOS technology and two power down modes (i.e., a standby mode and a data-retention mode). The microprocessor uses a switched substrate-impedance scheme to bias substrates in the standby mode while maintaining a 200-MHz operating speed. Data-retention capability during the standby mode is also maintained. This mode achieves 46.5-μA standby current. The microprocessor also offers a battery-backup capability in a self-substrate-biased data-retention mode. This makes it possible to apply a deep substrate bias without increasing the gate-induced drain leakage current or p-n junction current. The current consumption is only 17.8 μA when operating off a 1-V supply in the data-retention mode     

A 2000-MOPS embedded RISC processor with a Rambus DRAM controller

We have developed a 0.25-μm, 200-MHz embedded RISC processor for multimedia applications. This processor has a dual-issue superscalar datapath that consists of a 32-bit integer unit and a 64-bit single-instruction multiple-data (SIMD) function unit that together have a total of five multiply-adders. An on-chip concurrent Rambus DRAM (C-RDRAM) controller uses interleaved transactions to increase the memory bandwidth of the Rambus channel to 533 Mb/s. The controller also reduces latency by using the transaction interleaving and instruction prefetching. A 64-bit, 200-MHz internal bus transfers data among the CPU core, the C-RDRAM, and the peripherals. These high-data-rate channels improve CPU performance because they eliminate a bottleneck in the data supply. The datapath part of this chip was designed using a functional macrocell library that included placement information for leaf cells and resulted in the SIMD function unit of this chip's having 68000 transistors per square millimeter     

A 10-bit 200-MHz CMOS video DAC for HDTV applications

This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm². When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.     

A 1-V 10.7-MHz fourth-order bandpass /spl Delta//spl Sigma/ modulators using two switched op amps

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-/spl mu/m 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.     

A 200-MHz 64-b dual-issue CMOS microprocessor

A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75-μm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm×13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycle among scoreboarded integer, floating-point, address, and branch execution units. Power dissipation is 30 W at 200-MHz operation     

A Low-Jitter Polyphase-Filter-Based Frequency Multiplier With Phase Error Calibration

A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static phase error of the calibration circuit is 2.4 ps. The calibration leads to the normalized rms jitter of 0.049%.     

A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP)ULSI

The first single-chip 64-b vector-pipelined processor (VPP) ULSI is described. It executes vector operations indispensable to high-speed scientific computation. The VPP ULSI attains a 200-MFLOPS peak performance at a 100-MHz clock frequency. This extremely high performance is made possible by the integration on the VPP of a 64-b five-stage pipelined adder/shifter, a 64-b five-stage pipelined multiplier/divider/logic operation unit, and a 40-kb register file. Various new high-speed circuit techniques have been also developed for 100-MHz operations. The chip, which was fabricated with a 0.8-μm BiCMOS and triple-layer metallization process technology, has a 17.2-mm×17.3-mm area and contains about 693 K transistors. It consumes 13.2 W at a 100-MHz clock frequency with a single 5-V power supply     

250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI

A 250-MHz, 16-b, fixed-point, super-high-speed video signal processor (S-VSP) ULSI has been developed for constructing a video teleconferencing system. Two major technologies have been developed. One is a high-speed large-capacity on-chip memory architecture that achieves both 250-MHz internal signal processing and 13.5-MHz input and output buffering. The other is a circuit technology that achieves 250-MHz operations with a convolver/multiplier, an arithmetic logic unit (ALU), an accumulator, and various kinds of static RAMs (SRAMs). A phase-locked loop (PLL) is also integrated to generate a 250-MHz internal clock. The S-VSP ULSI, which was fabricated with 0.8-μm BiCMOS and triple-level-metallization technology, has a 15.5-mm×13.0-mm area and contains about 1.13 million transistors. It consumes 7 W at 250-MHz internal clock frequency with a single 5-V power supply     

A 900-MHz 1-V CMOS frequency synthesizer

A 900-MHz 1-V frequency synthesizer has been fabricated in a standard 0.35-μm CMOS technology. The frequency synthesizer consists of a divide-by-128/129 and 64/65 dual-modulus prescaler, phase-frequency detector, charge pump, and voltage-doubler circuit with an external voltage-controlled oscillator (VCO) and passive loop filter. The on-chip voltage-doubler circuit converts the 1-V supply voltage to the higher voltage which supplies the prescaler internally. In this way, the 900-MHz 1-V frequency synthesizer with an external VCO can be achieved. The measured phase noise is -112.7 dBc/Hz at a 100-kHz offset from the carrier, and the synthesizer dissipates 3.56 mW (not including VCOs) from a single 1-V supply when the switching frequency of the on-chip voltage doubler is 200 kHz and the power efficiency of the voltage doubler is 77.8%. The total chip area occupies 0.73 mm²     

A 200-MHz sub-mA RF front end for wireless hearing aid applications

A hearing-aid system with RF connection between both ear-pieces is described and its transceiver is introduced. A suitable 200-MHz RF front end has been implemented in a 0.8-μm BiCMOS technology. Low power consumption and area constraint were key requirements. The chip comprises a low noise amplifier (LNA), a single balanced mixer, a varactor tuned LC local oscillator with buffer and a 16/17 dual-modulus prescaler. The LNA has a measured gain of 17.5 dB at 200 MHz. The conversion g_m of the mixer is 1.88 mS. The overall voltage gain and noise figure are 26 dB and 5.2 dB, respectively. The voltage-controlled oscillator's (VCO's) phase noise is -104.7 dBc/Hz at an offset of 24 kHz     

A wide-band low-noise monolithic transimpedance amplifier

A transimpedance amplifier with nominal 200-MHz bandwidth, 6.6-k/spl Omega/ gain, and 33-nA RMS-equivalent input noise current is described. The circuit is realized in silicon-bipolar-monolithic technology and functions with source capacitances ranging from zero to several picofarads.     

A 220-mm2, four- and eight-bank, 256-Mb SDRAM withsingle-sided stitched WL architecture

A 220-mm², 256-Mb SDRAM has been fabricated in fully planarized 0.22-μm CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-μm WL pitch in limited space. An intraunit address increment pipeline scheme having two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single ended read-write-drive bus reduce the ICC₄ current to ~90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns. This design also uses a selectable row domain and divided column redundancy scheme that repairs up to ~1400 faults/chip with only 8% chip overhead     

Fundamental-Mode Pierce Oscillators Utilizing Bulk-Acoustic-Wave Resonators in the 250-- 300MHz Range (Short Papers)

Fundamental-mode Pierce oscillators in the 250-300-MHz range have been realized utilizing a unique form of a bulk-acoustic-wave (BAW) resonator. Phase noise greater than -100 dBc/Hz (1-kHz offset) has been extrapolated from data collected on oscillators operating at -22 and -24 dBm. Higher power levels to +6 dBm have been achieved. A linear-model design was used. The circuit topology used and resonator fabrication technique shows great promise for the creation of MMIC circuits in the 200-MHz-2-GHz range.     

Liquid crystal-based optical control of phased array antennas

Nematic liquid crystal (NLC) technology-based optical systems for controlling phased array antennas are presented. These systems can provide low-cost, high-quality (>6-b), phase-based antenna control for very large phased arrays (e.g. 5000 elements). An experiment demonstrating NLC-based antenna phase control is performed, with 0-3π phase shift measured for a 60-MHz carrier. A novel time-multiplexed radar beam scanning approach is introduced to counter the slow response of the NLCs, allowing fast 200 beams/s antenna scanning rates     

A 200-MHz CMOS x/sin(x) digital filter forcompensating D/A converter frequency response distortion

A 200-MHz 11-tap finite-impulse-response (FIR) digital filter for compensating the sin(x)/x spectrum distortion introduced by digital-to-analog (D/A) converters was designed and fabricated in a 1-μm CMOS technology. The chip core area is 1.91×3.28 mm² and its complexity is approximately 14,000 transistors. A fully parallel bit-level pipelined transpose-form carry-save architecture using simple powers-of-2 coefficients was used to achieve high throughput and low complexity. The various tradeoffs involving architecture selection, circuit design, and timing issues are presented, and the difficulties in realizing the speed potential of bit-level pipelined circuits are discussed     

A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply

A sample-and-hold amplifier designed for the front end of high-speed low-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz while allowing input/output voltage swings of 1.5 V with a 3-V supply. The circuit also incorporates a cancellation technique to relax the trade-off between the hold-mode feedthrough and the sampling speed. Fabricated in a 20-GHz 1-μm BiCMOS technology, an experimental prototype exhibits a harmonic distortion of -65 dB with a 10-MHz analog input and occupies an area of 220×150 μm². The measured feedthrough is -52 dB for a 50-MHz analog input and the droop rate is 40 μV/ns