内嵌SCR的LDMOS器件双骤回ESD特性研究

基于寄生参数分析,对内嵌SCR的LDMOS器件给出了二次骤回发生判据。本文对三种典型结构进行了数值仿真和比较,并基于此判据仿真优化了影响二次骤回的器件结构参数,从而提高器件ESD性能。TLP试验数据表明,当二次骤回电压由25.4V降低到8.1V时,器件ESD泄放能力由0.57A提高到3.1A。     

Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies

The impact of the base-pushout or Kirk-effect on the ESD characteristic of modern radio frequency (RF) NPN transistors is investigated. Due to the RF NPNs selectively implanted collector the onset of base-pushout is shifted to ESD relevant current levels, expressing itself in a characteristically high-ohmic breakdown mode after first snapback and a non-thermal second snapback, the so-called current mode snapback. Concepts to exploit the base-pushout effect for improved RF protection schemes are presented.     

Impact of snapback-induced hole injection on gate oxide reliabilityof N-MOSFETs

N-channel MOSFETs associated with CMOS output driver circuits are often driven deep into snapback during electrostatic discharge (ESD) events. The charge-pumping technique is used to show significant hole trapping in the oxide resulting from snapback bias conditions. Floating-gate measurements verify that significant hole current flows through the oxide during snapback. It is noted that snapback-induced hole injection can dramatically reduce gate oxide charge to breakdown and explains reduced hot-carrier lifetimes after snapback stress. Snapback stress results in oxide damage that is in many ways similar to that found during hot-carrier stress and radiation damage. These long-term reliability concerns limit the maximum allowable snapback current     

Integration of an SCR in an active clamp

This paper presents the integration of an SCR into a HV power clamp. For low currents the structure operates in “active clamp” mode and clamps the voltage to a value above the maximum operating voltage. After snapback the structure clamps the voltage to a low value as an SCR.     

一种新型的快速关断绝缘栅双极晶体管

本文提出了一种新型的快速关断绝缘栅双极晶体管。在关断的时候,器件用一个自己驱动的P型晶体管来短路发射极PN结。在没有引入如折返电流电压曲线等副作用和工艺困难的情况下,器件实现了低导通压降和快速关断。数值仿真表明关断时间从120ns降到12纳秒,同时并没有增加导通压降。     

0．13μm GGNMOS管的ESD特性研究

当ESD事件发生时,栅极接地NMOS晶体管是很容易被静电所击穿的。NMOS器件的ESD保护机理主要是利用该晶体管的骤回特性。文章对NMOS管的骤回特性进行了详细研究,利用特殊设计的GGNMOS管实现ESD保护器件。文章基于0．13μm硅化物CMOS工艺,设计并制作了各种具有不同版图参数和不同版图布局的栅极接地NMOS晶体管,通过TLP测试获得了实验结果,并对结果进行了。分析比较,详细讨论了栅极接地NMOS晶体管器件的版图参数和版图布局对其骤回特性的影响。通过这些试验结果,设计者可以预先估计GGNMOS在大ESD电流情况下的行为特性。     

埋栅型电力静电感应晶闸管的Ⅰ-Ⅴ特性反向转折机理

研究了静电感应晶闸管的反向转折特性.当工作在正向阻断态的阳极电压增大到某一临界值时,静电感应晶闸管的Ⅰ-Ⅴ曲线呈现出反向转折特性,甚至转向导通态.在综合考虑了工作机理、双注入效应、空间电荷效应、沟道中的电子-空穴等离子体和载流子寿命变化的基础上分析了静电感应晶闸管的反向转折特性.首次给出了反向转折机理的理论解释,并给出了估算转折电压和电流的数学表达式,在常用工艺参数范围内,计算结果和实验测量值基本一致.     

Characterization of bipolar snapback and breakdown voltage inthin-film SOI transistors by two-dimensional simulation

A two-dimensional finite-difference simulator for silicon-on-insulator (SOI) MOSFETs is presented. The simulator is derived from the MINIMOS4 simulator and incorporates additional features which permit the characterization of the bipolar snapback effect, which has been observed as a limiting feature in ultra-thin-film transistors. The snapback effect is illustrated as a hysteresis mechanism whereby, for a given bias condition, there are two different solutions to the semiconductor equations, depending on the starting condition. Examples of the application of the simulator to predict breakdown voltage in submicrometer devices are considered. Excellent agreement with measured values of breakdown voltage has been achieved for submicrometer n-channel transistors, both with and without the use of lightly doped drains     

埋栅型电力静电感应晶闸管的I-V特性反向转折机理

研究了静电感应晶闸管的反向转折特性．当工作在正向阻断态的阳极电压增大到某一临界值时,静电感应晶闸管的I-V曲线呈现出反向转折特性,甚至转向导通态．在综合考虑了工作机理、双注入效应、空间电荷效应、沟道中的电子一空穴等离子体和载流子寿命变化的基础上分析了静电感应晶闸管的反向转折特性．首次给出了反向转折机理的理论解释,并给出了估算转折电压和电流的数学表达式,在常用工艺参数范围内,计算结果和实验测量值基本一致．     

Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications

Because of its simple structure and snapback characteristics, the grounded-gate NMOS (GGNMOS) has been widely used as an electrostatic discharge (ESD) protection device. ESD performance of GGNMOS fabricated in the 65 nm CMOS process is investigated, and measurement results for the snapback behaviour, failure current It2, holding voltage, and trigger voltage of such advanced MOS devices are illustrated. The effects of four key GGNMOS parameters, channel length, finger number, drain-to-gate spacing and source-togate spacing on the ESD performance, are considered, and optimal MOS structures for robust ESD protection applications are suggested.     

一种可快速关断的新型横向绝缘栅双极晶体管

提出了一种可快速关断的新型横向绝缘栅双极晶体管(LIGBT)。在LIGBT关断时,利用一个集成的PMOS晶体管来短路发射结,以获得短的关断时间。PMOS晶体管由LIGBT驱动,不需要外部驱动电路。新器件在没有带来任何副作用(如snap-back现象和工艺制造上的困难)的情况下,获得了低的导通压降和快的关断速度。数值仿真结果表明,新器件在不增加导通压降的同时,将关断时间从120ns降到12ns。     

Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design

The double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.     

An Unassisted, Low Trigger-, and High Holding-Voltage SCR (uSCR) for On-Chip ESD-Protection Applications

A new silicon-controlled rectifier (SCR) is proposed and realized in a 0.35-mum/3.3-V fully salicided BiCMOS process for electrostatic-discharge (ESD) applications. Without using an external trigger circuitry, the unassisted SCR has a trigger voltage as low as 7 V to effectively protect deep-submicrometer MOS circuits, a holding voltage higher than the supply voltage to minimize transient influence and avoid latch-up issue, and a second snapback current density exceeding 60 mA/mum to provide robust ESD-protection solutions.     

用于电源线间ESD保护的新型高维持电压的SCR-LDMOS器件

The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD(electro-static discharge) clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.     

An analytical model for snapback in n-channel SOI MOSFET's

An analytical snapback model for n-channel silicon-on-insulator (SOI) transistors with body either tied to the source or floating is been presented. The snapback is modeled as a nonlinear feedback system leading to negative transconductances from which the jump in current can occur at the point of instability. The crux of this model is based on the strong dependence of the transistor threshold voltage on the body potential when the body potential is above the transistor surface potential at strong inversion. No parasitic bipolar action is invoked to account for the snapback phenomena. The model correctly predicts the occurrence of hysteresis/latch phenomena and the conditions under which the current jump occurs despite some gross approximations in the electric field and the injection level. Results obtained from this model show good agreement with experimental data measured from SIMOX devices fabricated on 0.3-μm epi film     

An advanced no-snapback LDMOSFET with optimized breakdown characteristics of drain n-n/sup +/ diodes

Snapbacks in sustain characteristics of lateral double-diffused MOSFETs (LDMOSFETs) are caused by positive feedbacks between the turn-on of the bipolar junction transistors (BJTs) and the avalanche breakdown of the drain n-n/sup +/ diodes . Although the n-n/sup +/ diodes are thus one of the most basic parasitic devices, which play a leading role in the snapback characteristics, neither a textbook nor a paper has ever described their breakdown characteristics in depth so as to realize a simple no-snapback LDMOSFET. This paper analyzes the snapback characteristics of n-n/sup +/ diodes and their mechanisms in detail. The no-snapback theory derived from this study is applied to an advanced no-snapback LDMOSFET with a simple structure, as an improved version of the conventional no-snapback LDMOSFET , which endures the electrostatic discharge (ESD) criterion for automotive applications: 15 kV, 150 pF, and 150 /spl Omega/.     

逆导型沟槽FS IGBT的设计与实现

逆导型沟槽场终止绝缘栅双极型晶体管(RC Trench FS IGBT)是一种新型的功率半导体器件,具有成本低、体积小、可靠性高等优点.设计并实现了一款1200V逆导型沟槽FS IGBT.重点研究了逆导型绝缘栅门极晶体管(RC IGBT)特有的回扫现象,以及如何从结构设计上消除回扫现象,其次,对RC IGBT在不同的载流子寿命下,进行了开关特性、反向恢复特性的仿真.研究结果发现随着载流子寿命的降低,其开关时间、反向恢复特性都有一定程度的改善.依据器件的最优化设计进行了流片.测试结果验证了不同设计对电流回扫现象的影响,以及不同少子寿命下导通特性和反向恢复特性的变化规律,器件的性能得到优化.     

Power capability limits of power MOSFET devices

With technology progression, power capability becomes a more critical concern in optimizing power device designs in various smart power IC applications. Interaction between the electrical and thermal entities is essential in understanding the power capability limit of the semiconductor devices in both transient and steady-state operations. This paper reports the fundamental mechanisms of the electrical–thermal coupling process during power dissipation and the characteristics of the power capability limits of the power MOSFET devices from the scope of intrinsic and extrinsic factors that affect the power capability. An electrothermally driven snapback breakdown is discussed in detail to investigate the physical mechanism of the power capability limits of an LDMOS power transistor. Both simulation and experimental results are in good agreement, indicating that the electrothermal snapback breakdown would occur at lower junction temperature than the intrinsic junction temperature.     

Double snapback in SOI nMOSFETs and its application for SOI ESDprotection

Double snapback in silicon-on-insulator (SOI) nMOSFETs is reported. An extensive experimental analysis of this phenomenon and a tentative model are presented. It is shown that this double-snapback phenomenon offers a basis for an electrostatic discharge (ESD) protection concept for SOI technologies     

Modeling of output snapback characteristics in n-channel SOIMOSFETs

The snapback effect is usually observed in the output characteristics of an n-channel SOI MOSFET with zero gate voltage in which the drain-to-source breakdown voltage is less than the drain-to-body avalanche voltage. It can be attributed to parasitic lateral bipolar actions as well as the MOS feedback mode of operation-a point often overlooked in the literature. An analytical model is developed for predicting the observed output characteristics taking into account both the bipolar and the MOS mechanisms. Results obtained from this model agree well with the experimental I-V curves, and show that, with continuing scaling of device geometries and improvement in SOI materials, the bipolar-induced snapback will become dominant in the future