Process improvement of 0.13 μm Cu/Low K (Black Diamond) dual damascene interconnection

Once fab develops a reliable integration scheme, the next step of process improvement and yield enhancement is very important for semiconductor industry, especially for the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection. In this paper, we discuss the process integration issues of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene integration. Solutions to the issues were explored and reported. Resist poisoning issue was solved by modifying photoresist and planarizing bottom-anti-reflective-coating (BARC) scheme. As a result there is an increase of 20% electrical yield. The impact of via etch time on interface of via bottom was studied and etch time was optimized for the best electrical performance of via chains. One of major targets of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene integration is the reliability improvement. It was observed that Cu cap etch results in different via chain profiles. Good profile of via chain is achieved after optimizing of Cu cap etch and via etch. The failure open rate of via chain and the highest dielectric breakdown field were also reported. The impacts of dual damascene cleaning on the reliability of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection was studied with splits between batch process and single wafer cleaning. On the whole, we successfully integrated 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection with good electrical and reliability performance after process improvement of patterning, via/Cu cap etch and dual damascene cleaning.     

300-mm Low-${hbox {k}}$ Wafer Dicing Saw Development

With the further shrinking of IC dimensions, low- material has been widely used to replace the traditional SiO interlayer dielectric (ILD) in order to reduce the interconnect delay. The introduction of low- material into silicon imposed challenges on dicing saw process. ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low- material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300-mm CMOS90-nm dual damascene low- wafer was chosen as a test vehicle to develop a robust low- dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street, etc.) affecting cutting quality were studied and optimized. The selected C90 Dual damascene low- device passed package reliability tests with the optimized low- dicing saw recipe and process. The further improvement and solutions in eliminating the low- dicing saw peeling were also explored.     

0.13μm铜互连工艺鼓包状缺陷问题的解决

传统集成电路制造工艺主要采用铝作为金属互连材料,但是随着晶体管尺寸越来越小,在0.13μm及以上制程中,一般采用铜大马士革互连工艺来提高器件的可靠性。铜互连工艺中需要用氮化硅作为穿孔图形蚀刻的阻挡层,由于氮化硅材质具有很强的应力,再加上制程中的热反应和蚀刻效应就会造成氮化硅层从界面掀起从而形成一种鼓包状缺陷(bubble defect)。文章通过调整并控制铜金属连线层间氧化电介质层的蚀刻速率,改变有机介质层(BARC)的沉积方法,以及改进产品的电路设计的检验规则,从而解决鼓包状缺陷的产生,降低产品芯片的报废率,提高产品的良率。     

SOD Stack Low-k Integration for 45nm Node and Beyond

We investigated single damascene integration with Porous MSQ (Methyl-Silsesqui-oxane, k value is 2.3) and Spin on Low k MSQ (k value is 2.9) as hard mask on Porous MSQ. Mechanical property of Low k material is improved by Electron Beam (EB) Cure technology. And also One time cure of stacked Low k is successful without any problem. On integration issue of Low k material, we demonstrated low damage resist strip process by using reducing gas chemistry and clarified mechanism of new Cu corrosion mode during CMP process.     

Study and improvement of electrical performance of 130 nm Cu/CVD low k SiOCH interconnect related to via etch process

130 nm technology uses Cu/low k dielectrics integration for the back-end-of-line (BEOL) process. The motivation of this work was to assess and improve the electrical yields of dense via chains through the study of effects of via etch process splits. We also demonstrate successful wafer fabrication of two Cu-level interconnects with chemical vapor deposited (CVD) low k SiOCH material using dual damascene architecture processed on 200 mm wafers. As a result, we achieved excellent wafer level electrical yields for both dense via chains and metal bridging-continuity structures of the BEOL interconnections.     

Rigorous diffraction simulations of topographic wafer stacks in double patterning

Double patterning is regarded as a potential candidate to achieve the 32 nm node in semiconductor manufacturing. A key problem for a standard litho-etch–litho-etch (LELE) double patterning process is to evaluate and tackle the impact of the wafer topography resulting from the hardmask pattern on the second lithography step. In this paper, we apply rigorous electromagnetic field (EMF) solvers to investigate the wafer topography effects. At first, the studied 3D mask is split into two masks. The topography resulting from the exposure with the first split mask is described by a patterned hardmask. Based on that, the bottom antireflective coating (BARC) thickness of the second wafer stack is optimized. Alternatively, a two beam interference and the full diffraction spectrum of the second mask are used as the illumination of the wafer stacks, respectively. Finally, simulated 3D resist profiles for different BARC thicknesses are shown. The importance of wafer topography impact, the optimization of topographic wafer stacks, and the possible solutions to compensate for the impact of the wafer topography are discussed.     

Linewidth control for 0.25 micron gate patterning

Linewidth control of small lines over non-planarized topography is particularly challenging due to resist thin film interference effects and reflective notching. This paper compares the linewidth control performance of several deep-UV resist processes, using dyed resist and both top and bottom anti-reflection coatings. Only the bottom anti-reflective coating (BARC) provides adequate linewidth control for development work on 0.25 micron gate patterning. The BARC and resist coating behavior over isolation topography is characterized using atomic force microscopy and correlated to residual linewidth variation. The performance of a zero bias etch process for BARC removal is also presented.     

用于注入层用途的湿法显影有机抗反射涂层

底部抗反射涂层(BARCs)和光刻胶已被广泛地用于半导体制造中的光刻加工工艺中。BARCs在光刻中的主要好处就是聚焦?曝光宽容度的改善,提高了关键尺寸的控制,消除了反射凹口,防止远紫外抗蚀剂由基底毒化。过去,BARCs主要被用于关键图层,例如栅和接触孔图层。但是随着集成电路特征尺寸的不断缩小,BARCs在注入层中的应用中由于基片表面形态引起的反射缺口和关键尺寸变化容差也变得更小,从而使BARCs的使用变得更为迫切。我们已成功开发了专门为注入层用途的湿法显影抗反射涂层。传统的干法刻蚀不适合用于注入层,因为它的工艺复杂而且在刻蚀过程中可能导致基片损坏。评述了产生注入光刻图层的工艺并讨论了湿法显影式抗反射涂层的设计标准和要求,同时还将讨论用于注入层光刻的湿法显影抗反射图层及其工艺的挑战。     

Aluminum dual damascene metallization for 0.175 μm DRAM generations and beyond (invited)

This paper presents an overview of issues associated with Al dual damascene process technology. Different integration schemes are discussed and characteristics of metal fill, planarization and reliability are highlighted. Finally, a comparison is made between Al dual damascene, Al RIE, and Cu dual damascene.     

SiLK™ etch optimization and electrical characterization for 0.13 μm interconnects

This paper is focused on the optimization of reactive ion etching (RIE) process of low-k polymeric spin-on dielectric (SOD) material, SiLK™ (Trade mark of Dow Chemical, USA), for 0.13 μm Cu-low-k interconnects technology and subsequent electrical characterization of the metallization. Damascene metallization of SiLK™ film was integrated with dual hardmask scheme and “trench first” approach. Etch processes for single damascene metal trench and dual damascene via and metal2 trench structures were developed and evaluated. Effect of SiN and SiC films used as one of the hard mask layers and copper cap layers for single and dual damascene formation were also evaluated. The advantages of using SiC over SiN layer as one of the (bottom) dual hardmask layers were demonstrated through the results of electrical performance. Integration issues related to process development were analyzed and discussed. Electrical and reliability performance of testing vehicles associated to different etch criteria were studied. Electrical yield of >90% was obtained for the structures under study, which indicated the wide process margin. The consistency of processes was further demonstrated through the successful integration of eight metal layers with SiLK™ dielectric film.     

Investigation of defect on copper bond pad surface in copper/low k process integration

In this work, inspection tools and surface analysis instruments were used to inspect and to analyze the defects at copper bond pads fabricated with copper/low k dual damascene deep submicron interconnect process integration. The defects at level are believed to be responsible for metal peeling at the Ta + Al and copper interface observed during chip wire bonding operation. The analysis results of the trace defects’ chemical composition show that the trace defects are the remainder of dielectric materials of passivation layer that is deposited on the top of the chip for protection. Copper oxide is also found to be present at the copper bond pads surface. A clear copper bond pad surface could be obtained using optimized dielectric pad window opening plasma etching conditions with suitable level plasma etching power and some overetch, improved photoresist stripping with oxygen and wet clean recipe with some chemicals. A clear copper bond pad surface will contribute to obtainment higher adhesion and lower contact resistance at Ta + Al and copper pad interface.     

Enhancement or reduction of catalytic dissolution reaction inchemically amplified resists by substrate contaminants

Chemical interaction of resist and substrate at the interface, which modifies the dissolution reaction, has degraded sidewall profile of resist features. Depending on the nature of the residue on the substrate, the “bottom pinching” (BP) effect and footing are observed, especially for chemically amplified (CA) resists. The BP effect is observed for CA resist on top of organic bottom antireflection coating (BARC). The BP effect is attributed to the acid generated from the underlying organic BARC. With optimization on softbake temperature of BARC, the BP effect is eliminated. On a silicon nitride surface, new chemical information has been obtained which explains “footing” and BP effects in CA resists. X-ray photoelectron spectroscopy (XPS) measurements indicate that the residual alkaline molecules on the nitride surface play a major role in the formation of footing. It appears that the organic contaminants are not responsible for footing. Less severe footing is observed if the nitride surface is plasma-deposited with a thin oxide cap, which suppresses the surface basicity. However, extended plasma deposition causes resist BP. This is ascribed to the surface acidity of a newly formed oxide cap, which enhances the CA resist development process. Results show that the N (1 s) peak, after extended plasma treatment, has shifted to a higher binding state, which suggests that the nitride surface becomes acidic, causing BP     

Copper-dielectric cap interface with enhanced reliability for 45 nm technology and beyond

A production capable preparation of a Cu-dielectric cap interface with a significantly enhanced reliability robustness has been developed for the 45 nm dual damascene technology and beyond. The electromigration (EM) lifetime could be improved by a factor of 2 with an advanced in situ cleaning process (ACP) including a soft silicidation step of the Cu metallization prior to the Cu-cap deposition. The increase of the Cu metal line resistivity can be controlled and limited to <6%. Anneal experiments at high temperature underline a high thermal stability of the Cu-cap interface including the copper-silicide (CuSi) intralayer. The new ACP is applicable to Cu interconnects built with dense or porous ultra-low-k (ULK) dielectrics because the process minimizes the surface damage. This yields in a doubled dielectric breakdown strength of a Cu damascene structure with a ULK inter-level dielectric by implementation of the ACP.     

New Gate CD Control Technology Using CF 4 Plasma Treatment Following HBr/O 2 Plasma Treatment Step in Gate Etch Process Using Organic BARC

A new technology of resist trimming in a gate etch process using organic bottom antireflective coating (BARC) for accurate and stable gate critical dimension (CD) control of sub-0.18-mum node technology is presented in this paper. The new method uses an in situ CF₄ plasma treatment following an HBr/O₂ plasma treatment step as a part of the gate etch process to achieve a stable gate CD. The new method controls gate CD by trimming the photo resist masking gate line by reducing the effect of etch by-products, the source of CD variation, after etching organic BARC with HBr/O₂ plasma. It shows the markedly improved gate CD capability over the conventional one using just an HBr/O₂ plasma treatment for the CD control. We confirm that this new method is very useful and effective for the accurate gate CD control for sub-0.18-mum node metal-oxide semiconductor technology     

A copper-dielectric cap interface with high resistance to electromigration for high performance semiconductor devices

In highly integrated semiconductor devices the time to failure of copper interconnects strongly depends on the properties of the copper-dielectric cap interface. In this work a production capable preparation of copper-dielectric cap interfaces with a high resistance to electromigration (EM) has been developed for 90 and 65 nm dual damascene technologies. With a new soft silicidation pretreatment of the copper metallization followed by a deposition of a SiCN or SiN cap the EM lifetime could be improved 3.5× referring to a standard SiCN capping process. The new pretreatment enables the formation of an epitaxial copper silicide layer on top of the copper metal lines which is seen as the key factor of the lifetime improvement. The new kind of cap layer process enables the lifetime improvement with only negligible increase of metal sheet resistance. The surface damage of copper and the low k inter-level dielectric which is typically caused during the copper precleaning could be minimized significantly. It is shown that there is no linear correlation between adhesion to copper and electromigration performance.     

Polymeric silicon-containing resist materials

Silicon-containing bilayer and trilayer photoresist technology is reviewed. Multilayer resist processes of this type rely on pattern generation in a thin imaging layer followed by pattern transfer to the thick planarising underlayer by oxygen reactive ion etching (RIE). The review concentrates on materials in which the silicon is an integral part of the polymer and does not specifically address photoresists where silicon is incorporated in a post-imaging process step (Such as top-surface-imaging resists). The review is not exhaustive but emphasizes instead specific examples of representative resist chemistry.     

A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.     

Rapid characterization and modeling of pattern-dependent variationin chemical-mechanical polishing

Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. In this work, we present new test mask designs and associated measurement and analysis methods to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects. An important goal of this approach is rapid learning which requires rapid data collection. While the masks are applicable to a variety of CMP applications including back-end, shallow-trench, or damascene processes, in this study we focus on a typical interconnect oxide planarization process, and compare the pattern-dependent variation models for two different polishing pads. For the process and pads considered, we find that pattern density is a strongly dominant factor, while structure area, pitch, and perimeter/area (aspect ratio) play only a minor role     

Single mask dual damascene processes

Single mask dual damascene processes are described. The unique mask merges via and modified trench patterns. We design the mask’s trench area to have partial transmission using thin chromium or add phase shifted gratings in the trench area to achieve destructive interference for lowering the intensity. Optical proximity correction is used to obtain the desired lithography process window. Upon exposure, the trench results in a partial exposure while the via is fully exposed and a dual damascene (DD) photoresist profile is created within specifications. Following with an integrated etch can complete the DD image transfer into the underneath dielectric. A single mask DD process eliminates via/trench misalignment issues, can save up to one half of metal mask cost, and 50% of other processing costs. It is expected to also boost yield and improve product reliability.     

Dense SiOC cap for damage-less ultra low k integration with direct CMP in C45 architecture and beyond

Deposited on a porous a-SiOC:H intermetal dielectric (IMD), a dense a-SiOC:H cap was successfully integrated in a C45 dual damascene architecture. The paper demonstrates that, stopping the CMP with around 10 nm of the cap left, the IMD integrity is preserved. As a consequence, a 3.5% decrease in RC delay, a 7.3% decrease in IMD integrated k-value and an increase of the time to failure by a 100 factor are reached relative to direct CMP. The cap also allowed to achieve straight lines and to improve the lines height uniformity as if CMP stopped on the IMD.