Deterioration of insulating films on silicon wafer due to surface charging during ion implantation

Charge-up phenomena during ion implantation were studied using the wafers (1) covered with the 1 μm thick photoresist and (2) fabricated with the MOS capacitor devices. The wafers were implanted with 35 keV As⁺ at the beam currents of 1 mA to 10 mA. The surface potential was measured by a capacitive probe set in the chamber. The ion distribution was also measured by a beam profile monitor placed behind the rotating disc. Surface charging on the photoresist wafers in some cases led to the puncture of the resist layer. Probe measurement showed that the charge-up phenomena were to a large extent governed by the behavior of the secondary electrons generated at ion implantation. The wafers with the MOS devices hardly failed by the charge build-up because of the bulk conduction through the thin oxide. However, the C-V measurement indicated that the deterioration of the oxide were influenced by the beam distribution.     

An evaluation of FUROX isolation technology for VLSI/nMOSFETfabrication

A defect-free near-zero bird's beak, fully recessed oxide (FUROX) field-isolation technology has been evaluated through the fabrication of VLSI/nMOSFETs. The FUROX process mainly consists of: (1) a thin nitrided oxide as the stress buffer layer and the interface sealing layer for local oxidation enhancement; and (2) a novel more-reliable nitride masking structure for a two-step field oxidation and a self-aligned field implantation. The elimination of the necking effect on positive photoresist and the improvement of critical dimension control for polysilicon gates using the planarized isolation have been demonstrated. Through electrical characterization of n⁺-p diodes and field and active transistors, the FUROX devices have been shown to provide low leakage-current level, good isolation property, and large recovery of the effective channel width (1.4 μm). Therefore, the serious narrow-width effects that exist in conventional LOCOS (local oxidation of silicon) isolated have been effectively reduced. Using histogram analysis, the reliability of the masking structure had hence good uniformity of device properties for FUROX isolation have been exhibited. The successful fabrication of FUROX devices with W_eff=0.6 μm clearly demonstrates that FUROX isolation technology is greatly superior to conventional LOCOS     

A metal-gate self-aligned MOSFET using nitride oxide

A new method for making metal-gate self-aligned transistors using a thin nitrided oxide (12 nm) as a gate dielectric has been demonstrated. The nitrided thermal oxide acts as both a local oxidation mask and the final gate dielectric to produce a self-aligned thick oxide in the source-drain region. The thick oxide reduces the overlap capacitance down to that of a self-aligned polysilicon-gate device while allowing the use of a metal gate with a much lower resistivity than the more commonly used polycrystalline silicon. A high-frequency capacitance-voltage technique has been used to measure gate to source-drain overlap capacitance. The overlap capacitance was measured for a range of source-drain oxide thicknesses from 370 down to 255 nm. The capacitance increased from 0.64 to 0.74 fF/µm. The overlap capacitance of a self-aligned polycrystalline silicon-gate device with similar processing parameters was 0.98 fF/µm. The channel mobility has been determined to be approximately 350 cm²/V . s. Transistors with channel lengths as low as 0.7/µm were fabricated. Ring oscillators were also fabricated with stage-delays as low as 300 ps at 1.5 V and power-delay products of 70 fJ.     

Charge retention improvement of charge-trapping type flash device by plasma immersion ion implantation

Electrical characteristics of charge trapping-type flash devices with HfAlO charge trapping layer nitrided by plasma immersion ion implantation (PIII) technique with different implantation energies and time are studied. Utilizing Fowler–Nordheim (FN) operation, the programming speed of flash memory with charge trapping layer nitrided at low implantation energy is faster than that of control sample. The erasing speed of PIII-treated sample is slightly slower than that of control one, which might be due to the formation of silicon nitride in the tunneling oxide. The retention characteristics of all PIII-treated samples are significantly improved. Different peak locations of implanted nitrogen concentrations are formed by different implantation energies, which cause various electrical characteristics of flash devices.     

A self-aligned nitrogen implantation process (SNIP) to minimizefield oxide thinning effect in submicrometer LOCOS

A self-aligned nitrogen implantation process (SNIP) utilizing low-energy and high-dose molecular nitrogen ions has been developed to minimize the field oxide thinning effect in submicrometer local oxidation of silicon (LOCOS) isolation. Molecular nitrogen ions with a dosage of 2.5×10¹⁶ cm^-2 were implanted at 20 keV into large isolation regions to selectively form a thin nitridelike layer which can effectively retard the thermal oxidation of silicon. Self-aligned spacers were developed to shield small-isolation regions from the nitrogen implantation. The oxidation rate in small-isolation regions was therefore not affected. The final field oxide thickness became more uniform for various isolation dimensions across the wafer. The device characteristics of the n- and p-MOSFET with the SNIP were similar to those of devices with the conventional LOCOS process. An increase in the magnitude of field threshold voltages at submicrometer isolation regions was measured for both n- and p-channel parasitic field-effect transistors with the SNIP. A minimal reduction in field oxide thickness of less than 10% and an acceptable field threshold voltage magnitude of higher than 7.5 V were achieved for an isolation width as narrow as 0.5 μm     

Direct moat isolation for VLSI

Device isolation is a major factor in determining the circuit packing density in VLSI. The scalability of device isolation by local oxidation of silicon (LOCOS) is limited by the large encroachment, including both physical and electrical, into the active device area resulting from lateral oxidation (bird's beaking) at the edge of isolation oxide and channel stop diffusion into the active device region. An alternative isolation technique is to form the active device area by patterning a thick field oxide uniformly grown or deposited on the silicon substrate. Such a direct moat isolation scheme makes more efficient use of the silicon area by reducing encroachment considerably and thus allowing closer packing of active devices than the LOCOS approach. Direct moat isolation process approaches for VLSI design rules are discussed. Short-channel effects on the subthreshold characteristics of the parasitic devices are studied using a two-dimensional model and compared with experimental measurements. Good device isolation is demonstrated in a parasitic device with a field oxide thickness of 550 nm and a minimum moat-to-moat spacing of 2 µm.     

Direct Moat Isolation for VLSI

Device isolation is a major factor in determining the circuit packing density in VLSI. The scalability of device isolation by local oxidation of silicon (LOCOS) is limited by the large encroachment, including both physical and electrical, into the active device area resulting from lateral oxidation (bird's beaking) at the edge of isolation oxide and channel stop diffusion into the active device region. An alternative isolation technique is to form the active device area by patterning a thick field oxide uniformly grown or deposited on the silicon substrate. Such a direct moat isolation scheme makes more efficient use of the silicon area by reducing encroachment considerably and thus allowing closer packing of active devices than the LOCOS approach. Direct moat isolation process approaches for VLSI design rules are discussed. Short-channel effects on the subthreshold characteristics of the parasitic devices are studied using a two-dimensional model and compared with experimental measurements. Good device isolation is demonstrated in a parasitic device with a field oxide thickness of 550 nm and a minimum moat-to-moat spacing of 2 /spl mu/m.     

A new fully recessed-oxide (FUROX) field isolation technology for scaled VLSI circuit fabrication

A more reliable process for near-zero bird's beak and fully recessed field isolation structure has been developed, which effectively reduces the narrow channel width effects which exist in the conventional local oxidation of silicon (LOCOS) processing. This proposed new process mainly consists of a new nitride masking structure for a two-step field oxidation and a self-aligned field implantation. Using a thin nitridized oxide as a buffer layer underneath the oxidation mask, the bird's beak of the first field oxide is largely reduced by the nitridation-enhanced interface sealing ability. No additional masking steps are required. The MOSFET's with various channel widths have been fabricated and characterized, and comparisons between the new isolation technique and the conventional LOCOS have been made. The improvement in device performance using the proposed isolation technique in MOS/VLSI fabrication is also clearly demonstrated.     

Effect of capping silicon nitride layer and nitrided gate oxide on hump of transistors

In this letter, we investigate the effect of capping silicon nitride and nitrided gate oxide on the hump in the sub-threshold slope of various transistors. Silicon wafers having both high- and low-voltage transistors are fabricated. The thin gate oxide is grown by nitric oxidation, while two step process of dry oxidation and low-pressure chemical vapor deposition (LPCVD) is used for the thick gate oxide. Note that the thickness of thin gate oxide is 4.5 nm, and 29 nm for thick gate oxide. It appears that both low-voltage nMOS and pMOS do not show any hump, nor does high-voltage pMOS. The subthreshold hump of high-voltage nMOS depends on process conditions. It shows severe hump without capping silicon nitride layer due to moisture diffusion during thermal anneal after interlayer oxide deposition by LPCVD. It also appears that nitrided oxide is effective to prevent hump by stopping moisture diffusion.     

Nitrogen Implantation to Improve Electron Channel Mobility in 4H-SiC MOSFET

Normally off 4H-SiC MOSFET devices have been fabricated on a p-type semiconductor and electrically characterized at different temperatures. A gate oxide obtained by nitrogen ion implantation performed before the thermal oxidation of SiC has been implemented in n-channel MOSFET technology. Two samples with a nitrogen concentration at the SiO₂/SiC interface of 5 X 10¹⁸ and 1.5 X 10¹⁹ cm^-3 and one unimplanted sample have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. For increasing temperature, in all the samples, the threshold voltage decreases, and the electron channel mobility increases. The latter case attains a maximum value of about 40 cm²/V ldr s at 200degC for the sample with the highest N concentration. These trends are explained by the reduction of interface electron traps in the upper half of the band gap toward the conduction band edge. These results demonstrate that N implantation can be effectively used to improve the electrical performances of an n-type surface channel 4H-SiC MOSFET.     

Transmission electron microscope study of oxidation-induced

Boron-implanted silicon devices have been shown to be affected by the ambient conditions during implantation, anneal and drive-in diffusion. The presence of oxygen appears to be of major significance. This study was undertaken to observe directly by transmission electron microscopy defects existing in silicon implanted and annealed under varying conditions which might account for changes in device characteristics. Boron ions at doses of 10¹³ to 10¹⁶ B⁺ /cm² were implanted at 180KeV into silicon through 2000Å. thick oxide layers formed by steam at 950°C or dry oxygen at 1150°C. After implantation specimens were annealed to 950° or 1000°C for 1/2 hour periods in dry nitrogen or argon. At 950°C precipitate colonies were found in the steam-oxidized specimens and were also present in those annealed to 1000 C, whereas, to date, no such colonies were found on the specimens which had been oxidized in dry oxygen at 1150°C. Energy dispersive x-ray analysis in an electron microscope shows that the particles contain copper and are possibly a copper suicide. Precipitation occurs only along dislocations formed on annealing the ion-damaged specimens Colonies were found as deep as 0.5μm below the oxide film. Tentatively, it is proposed that precipitation of the copper is observed only in specimens implanted through the steam formed oxide because of an increase in the number of silicon oxide nuclei due to the faster rate of oxidation. These nuclei form at dislocations and become nucleation sites for copper precipitation. The source of the copper contamination has not yet been determined.     

A silicon carbide LOCOS process using enhanced thermal oxidation by argon implantation

A process is described for creating local oxidation of silicon structure (LOCOS) structures in silicon carbide using enhanced thermal oxidation by argon implantation. Thicker oxides were created in selective regions by using multiple energy argon implants at a dose of 1 × 10¹⁵ cm⁻² prior to thermal oxidation. Atomic force microscopy was used to analyze the fabricated LOCOS structure.     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

Neutralization of electrically active aluminum in recrystallized silicon-on-sapphire films

We report the effect of steam oxidation at 875° C on the electrical resistivity, crystalline quality (measured by ion channeling), and Al concentration (measured by secondary ion mass spectrometry) in 0.25 μm thick, Si-implanted and recrystallized, Si-on-sapphire films. After a deep Si implantation (180 keV, 1.4×l0¹⁵ Si/cm²) at room temperature, and solid-phase epitaxial regrowth from the non-amorphized, 0.03 μm thick surface region, the initially undoped SOS films become doped p-type, and their resistivity decreases from (1−5)xl0¹⁴ ficm to 0.5 Ωcm. The doping is due to electrically active Al, released from the A1₂O₃ by the Si implantation, and present in the recrystallized films at a concentration of ≃2×l0¹⁶ Al/cm³ . After a 75 min steam oxidation at 875 °C, which consumes 0.06 Μm of Si, the resistivity of the recrystallized films increases to over 40 Ωcm, but the Al concentration is unchanged. The oxidation also uncovers higher quality material below the non-recrystallized surface layer. A semi-quantitative model is proposed to explain the electrical data, based on the diffusion of oxygen from the Si/SiO₂ interface into the SOS film during oxidation, and the formation of Al-O-Si neutral complexes. Data on the stability of the high-resistivity films against high-temperature annealing or re-amorphization and annealing is given.     

Improved electrical characteristics of high-k gated MOS devices by nitrogen incorporation with plasma immersion ion implantation (PIII)

High-k gate dielectric process is the key technology for nano-scale MOS device. A nitridation treatment on silicon surface is promising for characteristic improvement on high-k dielectric. It is found in this work that the electrical characteristics of high-k gated MOS devices can be improved by a nitridation treatment at silicon surface using plasma immersion ion implantation (PIII) at low ion energy and with a short implantation time. A shallow nitrogen profile at Si surface is known to be favorable for further enhancement of device properties.     

A novel processing technique to fabricate planar InGaAsP/InP electroabsorption waveguide modulators

A novel processing technique has been developed to fabricate planar electroabsorption waveguide modulators in compound semiconductor heterostructures. The lateral confinement of light is achieved by introducing controllable, reproducible, and stable stresses into semiconductor heterostructures using WNi surface stressor stripes, which also serve as electrodes for the waveguide modulators. Self-aligned helium implantation is employed to achieve electrical isolation using the Stressors as the templates for the ion masks. An increase as large as 33000 times has been obtained in the dc resistance between the neighboring waveguide modulators 25 μm apart. Propagation loss of 1.7 dB/cm is observed in the photoelastic waveguides at a wavelength of 1.53 μm following the He implantation. A post-implant thermal annealing at 310°C for 40 min increases the dc resistance between the neighboring devices to the maximum value, and at the same time reduces the optical loss to its value before ion implantation (less than 1 dB/cm). Using a combination of the photoelastic effect and helium implantation, planar InGaAsP/InP Franz-Keldysh-effect waveguide modulators 430 μm long with a 10 dB extinction ratio at 3 V for the TM mode have been fabricated. Planar electroabsorption quantum-confined Stark effect waveguide modulators have also been demonstrated. This planar device processing technique may prove valuable in future photonic integrated circuit technology.     

High-voltage accumulation-layer UMOSFET's in 4H-SiC

A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 μm drift region), a specific on-resistance of 15.7 mΩ-cm ² at room temperature, and a gate oxide field of 3 MV/cm     

Simox technology and its application to CMOS LSIS

SIMOX technology has been developed for fabricating SOI-type devices. In this technology, buried silicon oxide is used for the vertical isolation of semiconductor devices. The buried oxide is formed by oxygen-ion implantation into silicon, followed by epitaxial growth of silicon onto the surface of the residual silicon above the buried oxide. The crystallinity of the residual silicon was investigated by electron beam diffraction, while the implanted oxygen depth profile was analyzed by Rutherford backscattering spectroscopy. A 1Kb CMOS static RAM has been fabricated using polysilicon gate SIMOX technology with a 1.5μm effective channel length. The chip-select access time of the RAM was 12ns at 45mW dissi-pation power.     

The investigation of key technologies for sub-0.1-μm CMOS devicefabrication

The fabrication of sub-0.1-μm CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p⁺/n⁺ poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-μm poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-μm CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-μm CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved     

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET’s ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor （p-MOSFET） is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si （LT-Si）/10nm S i buffer was grown by Molecular Beam Epitaxy （MBE）, in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET＇s （L=4.2μm） transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm^2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.