A $K$ -Band CMOS Distributed Doubler With Current-Reuse Technique

A $K$-band distributed frequency doubler is developed in 0.18 $mu{rm m}$ CMOS technology. This doubler combines the distributed topology for broadband characteristics and current-reuse technique to improve the conversion gain. The high-pass drain line and high-pass inter-stage matching network are used to obtain a good fundamental rejection. A measured conversion gain of better than ${- 12.3}~{rm dB}$ is obtained, and the fundamental rejection is better than 30 dB for the output frequency between 18 and 26 GHz. The dc power consumption is 10.5 mW with a chip size of 0.55$,times,$0.5 ${rm mm}^{2}$.      

A Broadband Balanced Distributed Frequency Doubler With a Sharing Collector Line

A broadband balanced distributed frequency doubler fabricated by 0.35 $mu$m SiGe BiCMOS technology is developed to operate from 4 to 18 GHz output frequency. This balanced doubler consists of an active balun and a distributed doubler. A sharing collector line is used in the balanced distributed doubler to reduce the chip size. This circuit exhibits a measured conversion loss of less than 8 dB and a fundamental rejection of better than 23 dB for the output frequency between 4 and 18 GHz. The chip size is 1.1$, times ,$0.7 mm $^{2}$.      

A minaturized broad-band MMIC frequency doubler

A miniaturized broadband balanced MMIC (monolithic microwave integrated circuit) frequency double, composed of a common-gate FET and a common-source FET directly connected to each drain electrode, has been proposed and demonstrated. The doubler is designed and fabricated as a miniaturized function module using a conventional two-gate FET configuration, active trapping, and active impedance matching. The doubler design has been performed through phase error estimation, gate width optimization, and gate-source voltage optimization. The phase error estimation in a nonlinear condition has eliminated phase error compensation circuits. The fabricated chip size is only 0.5 mm×0.5 mm, which is about 1/10 the area of previously reported doublers. A conversion loss of 8-10 dB, a fundamental frequency suppression better than 17 dB, and an input return loss better than 8 dB are obtained in the output frequency range from 6 to 16 GHz. The broadband doubler as a miniaturized MMIC function module can be applicable to small-size oscillator MMICs and multifunction MMICs     

3 mm二倍频器的设计与实现

设计了一种W波段二倍频器,输入为46～48 GHz,输出为92～96 GHz,用来为毫米波接收前端系统提供3 mm本振信号.二倍频器采用微带线制作,且输入和输出端口位于腔体轴向两侧,选择对脊鳍线过渡来完成波导-微带的过渡结构.采用电磁场电路设计软件ADS,大大提高了毫米波电路设计的效率和准确度.测试结果表明,在输出92～96 GHz频带范围内,倍频损耗在22 dB以内.基波和三次谐波的抑制大于24 dB.该二倍频器符合工程使用的标准,同时其设计过程也表明了计算机辅助设计在毫米波电路设计方面是非常有价值的,可以大大提高工作效率.     

一种超宽带毫米波倍频器设计

叙述了一种超宽带毫米波倍频器的设计,该倍频器由有源差分balun级、对管倍频级和分布式功率放大级三个部分组成。在30—50GHz输出频率范围内,倍频器具有5dB的变频增益,输出功率大于13dBm,基波抑制大于15dB。     

An ultra-wideband MMIC balanced frequency doubler usingline-unified HEMTs

A very small, ultrawideband, MMIC balanced frequency doubler that uses line-unified HEMT configurations is proposed. A chip size of 1.0 mm×0.9 mm is achieved with a conversion loss of 8-10 dB in the 4-40-GHz output harmonics frequency range and fundamental frequency signal isolation of better than 21 dB above the input fundamental frequency of 7 GHz. Circuit parameters are optimized in a novel and simple prediction using an equation derived from the HEMT's DC characteristic and a linear-state CAD software package. The doubler has promise for realizing miniaturized, wideband MMIC transmitters/receivers     

Millimeter Wave Varistor Mode Schottky Diode Frequency Doubler in CMOS

The first mm-wave varistor mode Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler exhibits 14 dB conversion loss, $-11~{rm dBm}$ output power at 132 GHz and 6 GHz 3-dB output bandwidth from 128 to 134 GHz. The input matching is better than $-10~{rm dB}$ and the rejection of fundamental signal at output is greater than 14 dB from 62 to 70 GHz.      

A 25–75 GHz Miniature Double Balanced Frequency Doubler in 0.18-$mu$m CMOS Technology

A 25-75 GHz compact double balanced frequency doubler fabricated in standard 0.18-mum CMOS process is demonstrated. The resistive doubler is composed of two identical asymmetric broadside-coupled baluns, and a quad GS-connected diode. The fabricated doubler achieves a radio frequency bandwidth from 25 to 75 GHz with a maximum output power better than +3 dBm; the fundamental signal rejection is ranging from 32 to 59 dB, and only occupies a chip size of 0.24 mm². To the knowledge of the authors, this double balanced frequency doubler is the first demonstration with an operating frequency up to 75 GHz in 0.18-mum CMOS technology and shows this silicon-based frequency doubler can compare with its GaAs counterpart.     

2-20GHz宽带倍频器研究

研制了一种2～20GHz超宽带微波倍频器。该倍频器的核心是四只性能一致的肖特基势垒二极管形成的桥形堆,输入、输出电路则采用了适于宽带匹配的巴伦结构。在要求的频段范围内达到的指标：变频损耗优于15dB,典型值10dB;基波隔离优于25dB,典型值30dB;三次谐波抑制优于29dBc,典型值为35dBc。测试表明,该倍频器具有良好的可靠性和可重复性。     

125-GHz Diode Frequency Doubler in 0.13-$mu{hbox {m}}$ CMOS

The first mm-wave Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler built in 130-nm CMOS uses a balanced topology with two shunt Schottky barrier diodes, and exhibits $sim$10-dB conversion loss as well as $-$1.5-dBm output power at 125 GHz. The input matching is better than $-$10$~$dB from 61 to 66 GHz. The rejection of fundamental signal at output is greater than 12 dB for input frequency from 61 to 66$~$GHz. The doubler can generate signals up to 140 GHz.      

Design of 20-44 GHz broadband doubler MMIC

This paper presents the design and performance of a broadband millimeter-wave frequency doubler MMIC using active 0.15 μm GaAs PHEMT and operating at output frequencies from 20 to 44 GHz. This chip is composed of a single ended-into differential-out active Balun, balanced FETs in push-push configuration, and a distributed amplifier. The MMIC doubler exhibits more than 4 dB conversion gain with 12 dBm of output power, and the fundamental frequency suppression is typically -20 dBc up to 44 GHz. The MMIC works at VDD = 3.5 V, VSS = -3.5 V, Id = 200 mA and the chip size is 1.5 ×1.8 mm2.     

A Broadband CMOS Frequency Tripler Using a Third-Harmonic Enhanced Technique

A third harmonic enhanced technique is proposed to implement a broadband and low-phase-noise CMOS frequency tripler. It nonlinearly combines a pair of differential fundamental signals to generate deep cuts at the peaks of the fundamental waveform, resulting in a strong third harmonic frequency output. This mechanism has inherent suppression on the fundamental and the other harmonics so that only a low-Q high-pass filter on the lossy silicon substrate is applied at the output to further reject the fundamental and the second harmonic frequencies, in contrast to the high-Q filters used in most of the previous tripler designs. The fabricated circuit using 0.18 m CMOS technology is compact and has an input frequency range from 1.7 GHz to 2.25 GHz, or an output frequency range from 5.1 GHz to 6.75 GHz, resulting in about 28% frequency bandwidth. The optimum conversion loss from the tripler is 5.6 dB (27.5% efficiency) at an input power of 2 dBm. The suppressions for the fundamental, second and fourth harmonics in the measurement are better than 11 dB, 9 dB, and 20 dB within an input power range from 2 dBm to 7 dBm.     

宽带毫米波四倍频器

对毫米波宽带四倍频器的设计方法并进行了理论分析及计算仿真。介绍了利用平衡式结构对奇次谐波进行抑制,从而实现宽带偶次倍频的原理,提出了选择肖特基二极管的原则。利用HFSS仿真和优化电路结构,采用微带线鳍线结构实现了宽频带的毫米波二倍频器。在此基础上,采用两级倍频的方式实现了宽带毫米波四倍频器。设计的Ka波段毫米波四倍频器输入频率6.625～10 GHz,输入功率为10 dBm时,在26.5～40 GHz频率范围内,输出功率大于10 dBm,对三次和五次谐波的抑制大于20 dBc。     

A MMIC Doubler Based on Novel Open/Short Stub Hybrids

A new configuration of a balanced frequency PHEMT monolithic microwave integrated circuit doubler using open/short stub hybrids is proposed. With multi-coupled lines technology, the phase shifter is produced and applied to a Ka-band doubler successfully. As compared to the conventional lumped-element doubler, this phase shifter can make the doubler more compact in size and flexible in design. The doubler achieves an operation band width of 23 to 26 GHz with the best conversion loss of 7.4 dB at 25 GHz. In addition, the fundamental frequency suppression is better than 24.1 dB, and the chip dimension is as small as 0.85 times 1.1 mm².     

一个DC-32GHz两位微机械移相器

采用分布式微机械传输线结构实现了两位移相器,并且为了减小传输线负载电容和驱动电压首次提出了用共面波导传输线来驱动微机械桥的结构(共面波导驱动结构).结果显示驱动电压小于20V,20GHz时两位移相器的相移为0°/20.1°/41.9°/68.2°,插入损耗为-1.2dB.在DC到32GHz的范围内相移具有良好的线性,插入损耗小于-1.8dB,反射损耗好于-11dB.实验结果表明了该结构在高介电常数衬底上制造低插损、宽带数字微机械射频移相器的潜力.     

GaAs pHEMT工艺6～18GHz有源倍频器MMIC

基于GaAs pHEMT工艺,设计了一个6～18 GHz宽带有源倍频器MM IC,最终实现了较高的转换增益和谐波抑制特性。芯片内部集成了输入匹配、有源巴伦、对管倍频器和输出功率放大器等电路。外加3.5 V电源电压下的静态电流为80 mA;输入功率为6 dBm时,6～18 GHz输出带宽内的转换增益为6 dB;基波和三次谐波抑制30 dBc。当输出频率为12 GHz时,100 kHz频偏下的单边带相位噪声为-143 dBc/Hz。芯片面积为1 mm×1.5 mm。     

A 3–50 GHz Ultra-Wideband PHEMT MMIC Balanced Frequency Doubler

A novel configuration of ultra-wideband (UWB) GaAs PHEMT monolithic microwave integrated circuit balanced frequency doubler is presented. By using two different terminal impedances of the common-source/common-gate active balun, the doubler exhibits UWB characteristic with more than a four octave frequency range. From 3 to 50 GHz, the measured conversion gain and fundamental frequency suppression of the doubler are better than $-4$ dB and 15 dB.      

一种毫米波超宽带平面倍频器的设计

介绍了一种小型毫米波超宽带平面倍频器。其频带带宽达到三个倍频程,最高工作频率超过42GHz,倍频损耗为10dB±2．2dB,信号抑制不小于10dBc,输入功率动态范围为8dBm～20dBm,具有宽频带、高效率和大动态等特点,可以广泛应用在小型化毫米波平面电路中。     

单片集成GaAs MESFET微波开关——Ⅱ、宽带单刀单掷和单刀双掷开关电路

本文介绍了单片集成GaAs MESFET微波开关的设计方法和制作工艺.利用空气桥和通孔接地等工艺技术,研制成的调配型宽带单刀单掷开关在0.01～7GHz内,插损为2～3.5dB,隔离度不小于32dB;分布型宽带单刀双掷开关在4.5～7GHz内,插损为1～2dB,隔离度不小于21dB,5GHz下的最大功率容量为3瓦.实验也证实电路的开通时间小于0.6ns.     

级联型单级分布式宽带单片功率放大器

报道了一个采用级联型单级分布式结构的宽带单片功率放大器的设计方法和研制结果。文中通过拓扑比较和人工传输线理论研究,分析出该功放设计的难点,并基于仿真实验,给出解决方案。最终研制的两级单片功放在6～18GHz频率范围内线性增益13.5dB,平坦度±1dB,输入输出驻波比均小于2。全频带上,饱和输出功率为300～450mW,功率附加效率大于15%。该宽带单片功率放大器在100mm GaAs MMIC工艺线上采用0.25μm功率pHEMT标准工艺制作,芯片尺寸为2.7mm×1.25mm×0.08mm。