SRAM激光微束单粒子效应实验研究

结合器件版图,通过对2 k SRAM存储单元和外围电路进行单粒子效应激光微束辐照,获得SRAM器件的单粒子翻转敏感区域,测定了不同敏感区域单粒子翻转的激光能量阈值和等效LET阈值,并对SRAM器件的单粒子闭锁敏感度进行测试.结果表明,存储单元中截止N管漏区、截止P管漏区、对应门控管漏区是单粒子翻转的敏感区域;实验中没有测到该器件发生单粒子闭锁现象,表明采用外延工艺以及源漏接触、版图布局调整等设计对器件抗单粒子闭锁加固是十分有效的.     

伪闭锁路径法的应用

在研究体硅CMOS器件的闭锁窗口现象时,发现了一种新的抗闭锁方法———伪闭锁路径法。文章介绍了这种方法的基本原理,开发了一种抗闭锁电路实例。运用计算机仿真分析技术开发的抗闭锁电路,可以实现体硅CMOS器件的闭锁抑制。“闪光I”瞬时辐照试验表明,该抗闭锁电路的触发阈值剂量率很低,只有1.3×104Gy(Si)/s,能够成功抑制单片机系统的辐射感应闭锁。     

用SOI技术提高CMOS SRAM的抗单粒子翻转能力

提高静态随机存储器（SRAM）的抗单粒子能力是当前电子元器件抗辐射加固领域的研究重点之一。体硅CMOS SRAM不作电路设计加固则难以达到较好抗单粒子能力,作电路设计加固则要在芯片面积和功耗方面做出很大牺牲。为了研究绝缘体上硅（SOI）基SRAM芯片的抗单粒子翻转能力,突破了SOI CMOS加固工艺和128kb SRAM电路设计等关键技术,研制成功国产128kb SOI SRAM芯片。对电路样品的抗单粒子摸底实验表明,其抗单粒子翻转线性传输能量阈值大于61．8MeV／（mg／cm^2）,优于未做加固设计的体硅CMOS SRAM。结论表明,基于SOI技术,仅需进行器件结构和存储单元的适当考虑,即可达到较好的抗单粒子翻转能力。     

抗辐射128kb PDSOI静态随机存储器

介绍在部分耗尽绝缘体上硅(PD SOI)衬底上形成的抗辐射128kb静态随机存储器.在设计过程中,利用SOI器件所具有的特性,对电路进行精心的设计和层次化版图绘制,通过对关键路径和版图后全芯片的仿真,使得芯片一次流片成功.基于部分耗尽SOI材料本身所具有的抗辐射特性,通过采用存储单元完全体接触技术和H型栅晶体管技术,不仅降低了芯片的功耗,而且提高了芯片的总体抗辐射水平.经过测试,芯片的动态工作电流典型值为20mA@10MHz,抗总剂量率水平达到500krad(Si),瞬态剂量率水平超过2.45×1011 rad(Si)/s.这些设计实践必将进一步推动PD SOI CMOS工艺的研发,并为更大规模抗辐射电路的加固设计提供更多经验.     

抗辐射128kb PDSOI静态随机存储器

介绍在部分耗尽绝缘体上硅(PD SOI)衬底上形成的抗辐射128kb静态随机存储器.在设计过程中,利用SOI器件所具有的特性,对电路进行精心的设计和层次化版图绘制,通过对关键路径和版图后全芯片的仿真,使得芯片一次流片成功.基于部分耗尽SOI材料本身所具有的抗辐射特性,通过采用存储单元完全体接触技术和H型栅晶体管技术,不仅降低了芯片的功耗,而且提高了芯片的总体抗辐射水平.经过测试,芯片的动态工作电流典型值为20mA@10MHz,抗总剂量率水平达到500krad(Si),瞬态剂量率水平超过2.45×1011 rad(Si)/s.这些设计实践必将进一步推动PD SOI CMOS工艺的研发,并为更大规模抗辐射电路的加固设计提供更多经验.     

基于130nm PD-SOI工艺存储单元电路的抗辐射加固设计

基于130 nm部分耗尽绝缘体上硅(SOI) CMOS工艺,设计并开发了一款标准单元库.研究了单粒子效应并对标准单元库中存储单元电路进行了抗单粒子辐射的加固设计.提出了一种基于三模冗余(TMR)的改进的抗辐射加固技术,可以同时验证非加固与加固单元的翻转情况并定位翻转单元位置.对双互锁存储单元(DICE)加固、非加固存储单元电路进行了性能及抗辐射能力的测试对比.测试结果显示,应用DICE加固的存储单元电路在99.8 MeV ·cm2 ·mg_1的线性能量转移(LET)阈值下未发生翻转,非加固存储单元电路在37.6 MeV·cm2·mg_1和99.8 MeV·cm2·mg_1两个LET阈值下测试均发生了翻转,试验中两个版本的基本单元均未发生闩锁.结果证明,基于SOI CMOS工艺的抗辐射加固设计(RHBD)可以显著提升存储单元电路的抗单粒子翻转能力.     

GaAs 10 bit DAC的抗辐射设计和实验

通过分析砷化镓(GaAs)器件的电离辐射剂量率辐照机理和效应,结合电路结构,描述了砷化镓10 bit数模转换器(DAC)的电离辐射剂量率辐射效应、抗辐射设计和辐照实验。在电路设计上,10 bit DAC由两个5 bit DAC组成,通过芯片内部合成10 bit DAC,有效降低了芯片面积和制造工艺难度;通过分析电路的电离辐射剂量率辐射效应,针对敏感电路进行局部电路的抗辐射设计,提高电路抗辐射能力;结合实验条件和器件引线分布,设计合理的辐照实验方案,开发辐照实验电路板,进行辐照实验,获得科学的实验结果,验证电路的抗辐射能力。实验结果表明该数模转换器能够抗3×1011rad(Si)/s剂量率的瞬时辐照。     

基于SOI工艺的二极管瞬时剂量率效应数值模拟

为研究SOI MOS器件中寄生PN二极管在瞬时剂量率辐射下产生的光电流效应,采用TCAD工具,对0.13μm SOI工艺的PN二极管进行建模,数值模拟了二极管光电流变化与不同瞬态γ剂量率辐照之间的关系。通过模拟PN+型、P+N型两种二极管结构在不同偏置电压、不同剂量率辐射下的抗瞬时剂量率辐射能力,可以得出当瞬时剂量率为1×1014rad(Si)/s时,二极管在辐照下产生的光电流增量为辐照前的20%左右。该结论为集成电路器件的抗瞬时剂量率设计与仿真提供了数值参考。     

低压差线性稳压器瞬时电离辐射试验方法

在核爆环境下,要求低压差线性稳压器(LDO)的输出电压能够快速恢复。本文定性分析了瞬时电离辐射后LDO的输出电压恢复时间与负载电阻的关系;在“强光一号”加速器上开展了相应的瞬时电离辐射效应试验研究。对比分析不同负载条件下的输出电压恢复时间,发现两者密切相关,通过合理调整输出负载电阻值,可以有效地减小瞬时电离辐射后电路的恢复时间。辐射试验结果表明,经过瞬时电离剂量率为1.0×1011 rad(Si)/s辐照后,采用适当负载的LDO的输出电压恢复时间可小于100 μs。     

基于TSV转接板的3D SRAM单粒子多位翻转效应

为了研究硅通孔(TSV)转接板及重离子种类和能量对3D静态随机存储器(SRAM)单粒子多位翻转(MBU)效应的影响,建立了基于TSV转接板的2层堆叠3D封装SRAM模型,并选取6组相同线性能量传递(LET)值、不同能量的离子(¹¹B与^4He、²⁸Si与¹⁹F、⁵⁸Ni与²⁷Si、⁸⁶Kr与⁴⁰Ca、¹⁰⁷Ag与⁷⁴Ge、¹⁸¹Ta与¹³²Xe)进行蒙特卡洛仿真。结果表明,对于2层堆叠的TSV 3D封装SRAM,低能离子入射时,在Si路径下,下堆叠层SRAM多位翻转率比上堆叠层高,在TSV(Cu)路径下,下堆叠层SRAM多位翻转率比Si路径下更大;具有相同LET值的高能离子产生的影响较小。相比2D SRAM,在空间辐射环境中使用基于TSV转接板技术的3D封装SRAM时,需要进行更严格的评估。     

不同剂量率LC54HC04RH电路的电离辐射效应

对 L C54HC0 4 RH电路在不同辐射剂量率进行了电离辐射实验。分析了该电路的阈值电压随辐射剂量率的变化关系。实验结果表明 :在辐射剂量率处于 3× 10 -4 Gy(Si) / s到 1.98×10 -1Gy(Si) / s范围内 ,辐射感生界面陷阱电荷随辐射剂量率的减少而增加。辐射感生界面陷阱电荷是导致该电路在空间辐射环境下失效的主要原因。     

A comparison of the radiation tolerance of the STC bipolar,CMOS and merged bipolar/CMOS processes

This paper reports an assessment of the tolerance of STC’s bipolar, CMOS and ‘merged’ bipolar/CMOS processes to gamma total dose, dose rate and neutron fluence radiation effects. The objective of the assessment was to characterise process performance under worst case and near to worst case criteria when subjected to nuclear radiation up to the tactical level in accordance with BS 9000. Total dose irradiation was performed on the bipolar, CMOS and BiCMOS technologies with 9 Mrads (Si), 10-12 krads (Si) and 10-30 krads (Si) performance levels reported, respectively. Under dose rate conditions, transient upset, latch-up and photocurrent are reported with latch-up immunity reported for the bipolar 2 process and simultaneous latch-up and transient upset reported for both the bulk CMOS and BiCMOS processes. Neutron fluence testing was performed with the onset of failure for the CMOS reported at the 5 × 10¹⁴ neutrons/cm level and onset of failure for the bipolar and BiCMOS reported in the range 5 × 10¹⁴ to 5 × 10¹⁴ neutrons/cm².     

Pulsed ionizing radiation recovery characteristics of MSI GaAs integrated circuits

GaAs Schottky Diode FET Logic Divide-by 8 circuits have been characterized for transient response when exposed to 20 ns FXR pulses at 25°C. A logic upset threshold of about 10⁸rad/s was observed. At dose rates of 2 × 10¹⁰rads/s, functional operation was restored in 5 µs. A discussion of logic upset mechanisms is presented, attempting to explain both short and long term recovery observations.     

Hybrid Integration Between Long Focus Microlens Array and IR Detector Array

A special method, named step simulation method, is proposed for fabricating Si microlens array to improve the performance of infrared focal plane array (IR FPA). The focus length of rectangle-based multistep microlens array with element dimension of 40 µm×30 µm is 885.4 µm by the method, which is much longer than the focus length of microlens array fabricated by conventional Fresnel binary optics technique., The large-scale 256×256 element microlens array is hybridintegrated with the PtSi Schottky-barrier IR FPA by optical adhesive. The test results show that diffractive spot size of the microlens is 17 µm×15 µm and the average optical response of the IR FPA is increased by a factor of 2.4.     

320×256 GaAs/AlGaAs量子阱红外探测器

采用n型GaAs/AlGaAs量子阱材料,反应离子刻蚀RIE设备进行光栅、像元分割刻蚀,制备了320×256格式的长波量子阱红外探测器,像元中心距30 μm,像元光敏面28 μm×28 μm,两像元间距2 μm,达到了目前国际上1k×1k量子阱焦平面探测器像元间距研制水平。通过对320×256阵列上设计的陪管区进行光电性能测试,平均黑体探测率1.66×109 cm·Hz/W-1,响应率89.6 mA/W。     

Flash存储器浮栅单元的总剂量效应统计性分析

针对核设施机电设备中控制系统存储单元耐辐射可靠性评价的需要,以国产NOR型Flash存储器为研究对象,对器件存储阵列浮栅单元的总剂量损伤阈值开展了实验研究。综合利用SMOTE算法和Bootstrap法建立了一种基于极小子样的器件耐辐照可靠性评价方法,对被测样品校验失效剂量进行了统计分析。实验结果表明,器件浮栅单元的主要失效模式为浮栅电荷损失造成的阈值电压降低,平均校验错误剂量为(631.89±103.64)Gy(Si)。统计分析表明,器件总剂量损伤阈值服从对数正态分布。基于SMOTE-Bootstrap的可靠性评价方法避免了传统Bootstrap再生样本过于集中的问题,可应用于极小子样的可靠性评价。     

日盲紫外焦平面探测器的抗辐射加固设计

设计了一款320×256元抗辐射日盲紫外焦平面阵列探测器,重点针对探测器的读出电路版图、积分开关偏置点、探测器芯片外延结构及器件工艺开展了抗辐射加固设计。对加固样品开展了γ总剂量和中子辐照试验和测试,试验结果表明样品的抗电离辐照总剂量达到150krad(Si),抗中子辐照注量达到1×10¹³n/cm²(等效1MeV中子),验证了抗辐射加固措施的有效性。     

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

The first experimental test of new DICE memory cells with the transistors spaced into two groups (Spaced Transistor Groups DICE—STG DICE), composed on a 65-nm CMOS static RAM proved their high upset resilience. The STG DICE memory cells have two communication wires between the two groups of transistors that made it possible to use the striping of groups of transistors to increase the distances between sensitive nodes of cells up to 2.32–3.09 μm at a small increase in cell area. The blocks of 65-nm 128 × 32-bit CMOS RAM cache and 32 × 64-bit multiport RAM based on the STG DICE cells are characterized by upset thresholds lying in the range of 3.55–4.05 nJ of the laser pulse energy with a pulse duration of 70 ps and diameter of the spot of 3.5 μm. These threshold values exceed the upset thresholds of 65-nm CMOS RAM on 6T memory cells by factors of 20 for RAM cache and 3.5 for multiport RAM. In STG DICE RAM multiple upsets are absent in contrast to RAM based on 6T-cells.     

The monos memory transitor: Application in a radiation-hard nonvolatile RAM

The MONOS (metal-oxide-nitride-oxide-silicon) device is a prime candidate for use as the nonvolatile memory element in a radiation-hardened RAM (random-access memory). The endurance, retention and radiation properties of MONOS memory transistors have been studied as a function of post nitride deposition annealing. Following the nitride layer deposition, all devices were subjected to 800°C oxidation step and some were then annealed at 900°C in nitrogen. The nitrogen anneal produces an increase in memory window size of approximately 40%. The memory window center of the annealed devices is shifted toward more positive voltages and is more stable with endurance cycling. Endurance cycling to 10⁹ cycles produces a 20% increase in memory window size and a 60% increase in decay rate. For a radiation total dose of 10⁶ rads (Si), the memory window size is essentially unchanged and the decay rate increases approximately 13%. A combination of 10⁹ cycles and 10⁶ rads (Si) reduces the decades of retention (in sec) from 6.3 to 4.3 for a ±23-V 16-μsec write/erase pulse.     

X- and gamma-ray hardness of floating-gate EEPROM technology asapplied to implantable medical devices

There is a growing need for the inclusion of nonvolatile memory within implantable medical devices in order to store product identification, operating parameters, calibration information, as well as patient and diagnostic data. Due to the critical nature of the application however, the data retention reliability is of utmost importance. In the case of nonvolatile memories, a source of concern regards their exposure to ionizing radiation as the result of diagnostic or therapeutic procedures performed on the patient. This paper reports on X- and gamma-ray experiments and calculations on a representative modern electrically erasable and programmable read-only memory (EEPROM) (Atmel 24C64). No transient upsets due to 150 kVp X-rays were observed in 10 unbiased and five biased DTU's up to the maximum achievable 27 rad(Si)/s for a total dose of 200 rad(Si). Unbiased parts had no failure to an average total-dose of 40.9 krad(Si). The lowest failure level observed for an unbiased part was 30.0 krad(Si). In the biased parts, the read-mode operating current increased as a function of total dose from 47 μA prior to exposure to 385 μA at 30 krad(Si). The mean highest no-failure level for 10 unbiased parts exposed to Co⁶⁰ gamma-rays was 36.9 krad(Si) with a sigma of 2.3. Five biased DUT failures occurred at a mean of 27.84 krad(Si) with a sigma of 2.42. The analysis of these data, in comparison to maximum therapeutic photon radiation doses suggest that floating-gate EEPROM technology is reliable in the presence of photon ionizing-radiation exposures typical of medical diagnostic and therapeutic environments