基于ARM7TDMI的SoC芯片的原型验证

验证是SoC（系统芯片）设计的重要环节,FPGA原型验证平台能以实时的方式进行软硬件协同验证,缩短SoC的开发周期,验证系统级芯片软硬件设计的正确性,降低SoC系统的开发成本。本文介绍了基于ARM7TDMI处理器核的SoC芯片设计项目,提出相应的FPGA软硬件协同设计与验证的方案,并在此SoC芯片开发过程中得以实施,取得良好效果。     

芯片安全架构平台设计研究

通过CPU选型及架构评估,构建了SoC芯片安全架构研究平台,实现了软硬件设计、FPGA原型验证及ASIC物理设计.在该平台上,可灵活实现和验证各种SoC的功能,对SoC产品的攻击与防护技术的安全性进行研究和分析.     

系统芯片的关键技术及发展方向

系统芯片,即(SoC),将包含处理器、存储器和片上逻辑等的一个系统集成在单一的芯片上。SoC所特有的功能强、速度高、体积小、成本低、功耗低等优点使得其技术不断发展,应用越来越广泛。文章首先探讨了系统芯片(SoC)的特点及分类,接着详细阐述了开发SoC所需IP核设计与复用、软硬件协同设计、软硬件协同设计等关键技术。分析了基于平台设计方法的优点,并介绍了SoC的一体化测试流程、共时测试等SoC测试新技术。     

系统原型验证平台助力SoC设计

系统原型验证是把IP提前在原型验证平台上验证通过后再进行芯片设计,它支持在FPGA上进行早期软硬件开发和测试验证,可提高SoC设计首次流片即成功的机率,缩短设计周期。     

基于SoC设计的软硬件协同验证技术研究

软硬件协同验证是SoC设计的核心技术。其主要目的是验证系统级芯片软硬件接口的功能和时序,验证系统级芯片软硬件设计的正确性,以及在芯片流片回来前开发应用软件。本文介绍了基于SoC设计的软硬件协同验证方法学原理及其验证流程。然后分析了SoC开发中采用的3种软硬件协同验证方案,ISS方案、CVE方案、FPGA／EMULATOR方案,对其验证速度、时间精度、调试性能、准备工作、价格成本、适用范围等各方面性能做出比较并提出应用建议。     

基于ARCA3 CPU的嵌入式SoC的FPGA原型验证

基于FPGA的验证是SoC功能验证的有效途径,建立一个基于FPGA的原型验证系统已成为SoC验证的重要方法.ARCA3是一种高性能、低功耗,国产的嵌入式微处理器.在ARCA3和AMBA架构上集成存储器控制器等IP核和外设,构建一个嵌入式SoC,并在FPGA上实现SoC的原型验证系统和软硬件协同验证环境.在FPGA原型机上运行Bootloader和操作系统,验证整个系统硬件的可操作性和软硬件之间的交互.基于FPGA的原型验证系统的实现可以快速验证基于ARCA3的各种抽象层次的IP核和开发基于ARCA3的软件应用.     

一种32 Bit SoC软硬件协同验证环境的实现

软硬件协同验证是系统芯片设计的重要组成部分。针对基于32 Bit CPU核的某控制系统芯片的具体要求,提出了一种系统芯片软硬件协同验证策略,构建了一个软硬件协同验证环境。该环境利用处理器内核模型支持内核指令集的特性运行功能测试程序,实现SoC软硬件的同步调试,并能够快速定位软硬件的仿真错误点,有效提高了仿真效率。该SoC软硬件协同验证环境完成了设计目的,并对其他系统芯片设计具有一定的参考价值。     

基于ARM SoC的FPGA原型验证

ARM是目前SoC设计中应用最为广泛的高性价比的RISC处理器,FPGA原型验证是SoC有效的验证途径,FPGA原型验证平台能以实时的方式进行软硬件协同验证,从而可以缩短SoC的开发周期,提高验证工作的可靠性,降低SoC系统的开发成本.     

SoC设计平台及应用实例

本文介绍了深亚微米SoC设计的关键技术、详述了苏州国芯的SoC设计平台--CSOC300的功能和基本原理,对平台中的软硬件协同仿真和验证进行了重点分析,并应用该平台成功的设计了一个产品--32位USB2.0控制器系统芯片CCM3106,对该款芯片的功能和结构进行了简要介绍.     

利用S2C Stratix Ⅳ TAI LM进行SoC原型验证的方法学

FPGA原型验证是一种在FPGA上搭建SoC和ASIC设计原型的方法学,可以方便的进行硬件验证和早期软件开发。此方法学也称为ASIC原型验证或SoC原型验证。在FPGA上搭建SoC和ASIC设计原型已经成为验证硬件设计和早期软硬件协同设     

多核CPU在HDTV SoC上的实现

以多核CPU在HDTV SoC上的应用为例,简述了HDTV SoC的功能模块划分.探讨了以同核异构方式互连的CPU之间的通信问题,同时还介绍了以此结构为基础的一次完整CPU通信过程.     

SoC设计中的低功耗策略

低功耗设计已经成为片上系统(SoC)设计的主题.当今的设计已经从过去的性能、面积二维目标转变为性能、面积和功耗的三维目标.本文深入探讨了片上系统设计中的低功耗设计策略,在晶体管和逻辑门级、寄存器传输级和系统结构级各设计抽象层次上阐述了低功耗设计所面临的问题,并给出了各级的低功耗优化策略.     

使用SystemC设计片上自演化系统

提出片上自演化系统的概念和基于SystemC的片上自演化系统设计方法,给出片上自演化系统的总体结构,使用SystemC建模搭建自演化系统实验平台.以典型低通切比雪夫滤波器为例,验证了实验平台的有效性.使用SystemC设计自演化系统既可在较高的抽象水平搭建自演化系统模型,加速验证、性能分析和探索系统结构,又可方便地进行软硬件协同设计,并最终达到硬件实现.     

Platform designer: An approach for modeling multiprocessor platforms based on SystemC

This paper[3.5pc] presents the Platform Designer (PD) framework, a set of SystemC based tools that provide support for modeling, simulation and analysis of multiprocessor SoC platforms (MPSoC), at different abstraction levels. PD provides mechanisms for interconnection specification, process synchronization and communication, thus allowing the modeling of a complete platform, in a unified environment. To do that it uses an extension of the ArchC ADL and acsys, a tool that enables the automatic generation of a SystemC simulator of the platform. The main advantages of this approach are twofold. First, designers have more flexibility since they can integrate and configure different processors to the platform, using a single environment. Second, it enables a faster design space exploration, given that it automatically generates SystemC simulators of whole platforms at distinct abstraction levels. A number of platform variations can be tried out with minor design changes, thus reducing design time. Experimental results show the suitability of the platform simulator for design space exploration. Real applications (with medium complexity) run in the platform in few minutes. Combined with the facility to generate platforms with minor changes, this feature allows an improvement of the design space exploration.     

基于FPGA的ARM SoC原型验证平台设计

基于FPGA的验证平台是SoC有效的验证途径,在流片前建立一个基于FPGA的高性价比的原型验证系统已成为SoC验证的重要方法。ARM嵌入式CPU是目前广泛应用的高性价比的RISC类型CPU核,文中主要描述了以FPGA为核心的ARM SoC验证系统的设计实现过程,并对SoC设计中的FPGA验证问题进行了分析和讨论。     

SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse

As the complexity of designing system-on-chips increases, so does the need to abstract low-level design issues to improve designer productivity. The reuse of previously designed Intellectual Property (IP) modules is a common form of abstraction used to reduce design time. However, different applications typically use a variety of physical interfaces, communication protocols, and global system-level control for IP modules, which complicates design reuse. In this paper, we describe the SIMPPL system model and an abstraction for IP modules, called the computing element (CE), that facilitate the SoC design for both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms. The CE abstraction decouples the datapath and system-level communication from the application-specific control to promote design reuse by localizing control redesign of IP for new applications. The SIMPPL model facilitates multi-clock domain SoC designs and expedites system integration by defining the intermodule links and communication protocols     

Performance Analysis of Arbitration Policies for SoC Communication Architectures

As technology scales toward deep submicron, the integration of a large number of IP blocks on the same silicon die is becoming technically feasible, thus enabling large-scale parallel computations, such as those required for multimedia workloads. The communication architecture is becoming the bottleneck for these multiprocessor Systems-on-Chip (SoC), and efficient contention resolution schemes for managing simultaneous access requests to the shared communication resources are required to prevent system performance degradation. The contribution of this work is to analyze the impact on multiprocessor SoC performance of different bus arbitration policies under different communication patterns, showing the distinctive features of each policy and the strong correlation of their effectiveness with the communication requirements of the applications. Beyond traditional arbitration schemes such as round robin and TDMA, another policy is considered that periodically allocates a temporal slot for contention-free bus utilization to a processor which needs fixed predictable bandwidth for the correct execution of its time-critical task. The results are derived on a complete and scalable multiprocessor SoC simulation platform based on SystemC, whose software support includes a complete embedded multiprocessor OS (RTEMS). The communication architecture is AMBA compliant, and we exploit the flexibility of this multi-master commercial standard, which does not specify the arbitration algorithm, to implement the explored contention resolution schemes.     

多电源混合电压SoC的全芯片ESD设计实例

SoC是含有微处理器、外围电路等的超大规模集成电路,具有器件特征尺寸小、复杂度高、面积大、数模混合等特点,SoC的ESD设计成为设计师面临的一个新的设计挑战。文章详细介绍了一个复杂的多电源、混合电压专用SoC芯片的全芯片ESD设计方案,并结合电路特点仔细分析了SoC芯片ESD设计的难点,提出了先工艺、再器件、再电路三个层次的分析思路,并将芯片ESD总体解决方案中的关键设计重点进行了逐一分析,最后给出了全芯片ESD防护架构的示意图。该SoC芯片基于0.35μm 2P4M Polycide混合信号CMOS工艺流片,采用文中提出的全芯片ESD防护架构,使该芯片的HBM ESD等级达到了4kV。