电子节能灯用高压铝电解电容器耐高温技术的研究

通过开发乙二醇、二甘醇及磷酸三丁酯混合溶剂,癸二酸铵与1,7-癸二酸铵的双溶质体系的工作电解液,并加入适量的添加剂,优选生产工艺,提高了电子节能灯用高压铝电解电容器的耐高温性能及耐大纹波电流特性,研制出的产品高温负荷达到130℃3000h。     

节能灯用铝电解电容器工作电解液配方研究

以十二双酸铵、对硝基苯甲酸、次亚磷酸和高分子添加剂PA四种组分为考察因素,采用单纯形法进行试验设计,研究了节能灯用铝电解电容器的工作电解液的配方.结果表明,当乙二醇质量分数(下同)为93%,癸二酸铵为4.14%,十二双酸铵为0.9%,对硝基苯甲酸为0.16%,次亚磷酸为0.2%,高分子添加剂为1.6%时,制备的铝电解电...     

一种新型有机金属化合物的三阶光学非线性研究

为了研究一种新型有机金属化合物(十六烷基三甲基铵)双(1,3-二硫杂环戊烯-2-硫酮-4,5-二硫基)-镍(简称CTNi)的三阶非线性光学性质,配制了浓度为1.0×10-4mol/L的丙酮溶液作为待测样品,采用Z扫描测试技术,在波长为1064 nm,脉宽为40 ps的条件下研究了该样品的三阶非线性光学性质.研究发现,该材料具有很强的饱和吸收特性,其激发态有效吸收截面为eσff=1.47×10-18cm2,相应的非线性吸收系数β=-4.36×10-12m/W.另外,Z扫描曲线显示该材料还具有较强的自散焦效应,其三阶非线性折射系数n2=-1.55×10-18m2/W.     

铝电解电容器用支链多碳二元羧酸铵电解液的研究

实验合成了支链多碳二元羧酸(SCPDA),并研究了其性能.结果表明:SCPDA的分解温度超过200℃,耐热稳定性比癸二酸好.相同条件下,支链多碳二元羧酸铵(SCPDAA)电解液的性能(030℃≈1.9×10-3 S/cm,Us=483 V,pH=6.0)比癸二酸铵电解液(σ30℃≈1.7×10-3 S/cm,Us=46...     

新型含硒杂环红光聚芴电解质的电致发光器件制备和研究

利用新型的聚[9,9-二辛基芴-9,9-(双(3′-(N,N-二甲基)-N-乙基铵 溴-)丙基)芴-4,7-二噻吩-2-基-2,1,3-苯并硒二唑](PFNBr-DBSe)共扼聚电解质制备了聚合物发光二极管。这类共扼聚电解质可用乙醇等溶剂成膜,不仅可代替传统的甲苯等芳香性非极性溶剂,而且有利于制备溶液型的多层显示器件。文章研究了这类新型聚电解质的光致发光特性及发光二极管器件的电荧光特性。研究表明在紫外光照射或电激发下,窄带系的DBSe链段通过俘获激子能够实现有效的能量转移。聚电解质中DBSe的含量在5%以上,其器件具有电致发光峰值为700~740nm的饱和红光发射。所制聚电解质器件在用铝作电极时的电致发光效率比用钡作电极时要高。     

一种金属有机配合物的光限幅性质研究

合成了一种金属有机配合物二(四甲基铵)双(1,3-二硫杂环戊烯-2-硫酮-4,5-二硫基)-铜(MeCu),配制了其浓度为2×10-3 mol/L的丙酮溶液,采用开孔Z扫描方法,分别测试了该样品溶液在波长为1064 nm,脉宽为40 ps和波长1053 nm,脉宽15 ns条件下的非线件光学特性.结果表明,该材料在皮秒光强下表现出双光子吸收,吸收系数为4×10-13 m/W,而在纳秒光强下,该材料具有很强的反饱和吸收特性,吸收系数为7.07×10-11 m/W.进一步研究了该材料在不同光强下的非线性吸收性质,发现其在纳秒光强下有很强的光限幅特性,测试了其在15 ns的光限幅特性,结果表明,该材料在光限幅应用上具有潜在应用价值.     

半导体双稳态激光器在光注入下的实验研究

本文报道了InGaAsP/InP 双区共腔脊形波导双稳激光器在外光注入下产生光-光双稳特性及光-光放大的实验结果,给出了器件在直流及脉冲工作时的光-光双稳特性,并对结果进行了初步分析.     

HPLC法测定复方托吡卡胺滴眼液中苯扎氯铵的含量

目的：建立超高效液相色谱法测定复方托吡卡胺滴眼液中苯扎氯铵的含量测定方法。方法：色谱柱为Alltech Alltima -CN（250cm ×4．6mm ,5μm）,流动相为0．1mol?L -1醋酸钠溶液（用冰醋酸调节pH值至5．0）-乙腈（60：40）,检测波长254nm ,流速为2．0ml?min -1,柱温30℃,进样体积50μL。结果：苯扎氯铵在0．02至0．5mg?mL -1浓度范围内线性关系良好（r＝0．9999）;平均回收率为98．91％,RSD＝0．44％（n＝9）。结论：该方法准确、简便、快速、可靠,能有效控制复方托吡卡胺滴眼液中苯扎氯铵的含量。     

AlCl_3水溶液和混合溶液中Al元素的双脉冲激光诱导击穿光谱

利用自建的液相射流和双脉冲激光诱导击穿光谱技术(LIBS)实验装置,测定了AlCl3水溶液和混合溶液中Al元素的单脉冲和双脉冲激光诱导击穿光谱,给出了单、双脉冲下的最优LIBS实验参数,在最优化实验条件下,得到AlCl3水溶液和混合溶液中Al元素质量分数的单、双脉冲LIBS检测限分别为26.79×10-6、28.85×10-6和11.93×10-6、14.46×10-6,双脉冲LIBS检测灵敏度比单脉冲明显提高。     

层状双氢氧化物及其复合材料在超级电容器领域的研究进展

近年来层状双氢氧化物研究发展势头迅猛,本综述归纳了层状双氢氧化物及其复合材料的制备方法,重点关注层状双氢氧化物在超级电容器领域的研究及前景。层状双氢氧化物的制备方法有共沉淀法、水热合成法及煅烧重构法等。层状双氢氧化物在超级电容器领域多以复合材料出现,如石墨烯-层状双氢氧化物,泡沫镍-层状双氢氧化物等,合成技术趋于成熟,电化学性能不断优化。     

新型基区结构高反压功率晶体管的优化

依据电参数指标要求,针对高压-高增益硅功率晶体管基区结构和终端结构进行优化研究。提出了一种可用于改善集电极-发射极击穿电压(V_(BRCEO))和电流放大倍数(β)矛盾关系的带埋层的新型基区结构,并针对埋层基区结构对高压-高增益硅功率晶体管电性能及可靠性的影响进行了研究。仿真结果表明:新型基区结构不仅可以很好地折中晶体管β与V_(BRCEO)之间的矛盾关系,而且还能在较大的埋层基区宽度、埋层基区掺杂峰值浓度范围内使晶体管获得较低且一致性较好的饱和压降;具有新型基区结构的晶体管在改善正偏的情况下抗二次击穿能力具有明显优势。由仿真得到的器件结构参数,研制出的样片的β,V_(BRCEO)和集电极-基极击穿电压(V_(BRCBO))均满足电参数指标要求。     

Optical methods of electrical measurement at high voltage levels

Optical methods to measure electric parameters and transmit the information from high voltage circuits to ground potential are described and evaluated in the light of the specific requirements of high-voltage measurement applications. The history and physics of a variety of optoelectrical methods found suitable for electrical measurement applications are introduced. Existing optical devices for measuring alternating, direct, and impulse currents and voltages in high-voltage circuits are reviewed with emphasis on the operation and features of several selected methods. The use of these techniques in industrial systems, in research laboratory apparatus, and in reference standards laboratories is discussed.     

高压LED球泡灯的设计与分段优化

近年来在解决以开关电源为基础的传统LED驱动效率低、体积大和成本高等问题的过程中,高压线性分段驱动技术应运而生。为了研究高压线性分段驱动LED球泡灯的设计方法,以高压线性分段驱动芯片SM2087为例,通过实测LED效率得到合适的分段比例为8∶4∶3∶1;并根据该分段比例设计了一种高压LED球泡灯,LED采用COB的方式布置在陶瓷环基板上,散热采用太阳花结构,驱动电路置于灯头内,其具有较高的效率、良好的散热与耐高压能力以及较大的发光角度。     

变频器用螺栓型铝电解电容器长寿命技术的研究

为了提高变频器用螺栓型高压大容量铝电解电容器的使用寿命、高温高压稳定性以及耐大纹渡电流冲击的特性．通过对工作电解液溶剂、溶质和添加剂的研究与分析,以及对原材料的优选和生产工艺的优化,研制出的产品105℃高温负荷达5000小时。     

Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 /spl mu/m and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180/spl mu/m2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of /spl plusmn/1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10/sup 4/ write/erase cycles.     

High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories

In order to scale high-voltage transistors for high-density negative-gate channel-erasing NOR flash memories, two circuit techniques were developed. A proposed level shifter with low operating voltage is composed of three parts, a latch holding the negative erasing voltage, two coupling capacitors connected with the latched nodes in the latch, and high-voltage drivers inverting the latch, resulting in reduction of the maximum internal voltage by 0.5 V. A proposed high-voltage generator adds a path-gate logic to a conventional high-voltage generator to realize both low noise and low ripple voltage, resulting in a reduction of the maximum internal voltage by 0.5 V. As a result, these circuit techniques along with high coupling-ratio cell technology can scale down the high-voltage transistors by 15% and can realize higher density negative-gate channel-erase NOR flash memories in comparison with the source-erase NOR flash memories.     

A 120-W Boost Converter Operation Using a High-Voltage GaN-HEMT

A boost converter with a 940-V/4.4 A GaN-HEMT as the main switching device was demonstrated to show the possibility of using high-voltage GaN-HEMTs in power electronic applications. The demonstrated circuit achieved an output power of 122 W and a power efficiency of 94.2% under a drain peak voltage as high as 350 V and a switching frequency of 1 MHz. The dual field-plate structure realized high-voltage switching operation with high power efficiency as dynamic on-resistance was suppressed by an increase of the current collapse phenomena.     

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm², a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10⁴write/erase cycles.     

Anwendungsorientierte F&E-Aktivit?ten der Kelag mit Bezug zur Hochspannungstechnik

Application-orientated research and development activities with special consideration to energy and high-voltage engineering have had a long standing relationship within the energy industry and have always had high relevance. New challenges over the past decade have led to an intensification of the activities and strengthened co-operation between energy utilities, universities and research institutions. In order to demonstrate this, Kelag selected research topics will be presented from the field of high voltage engineering. In the context of the challenges to future energy systems and with respect to flexibility, energy storage and plant availability the relevance to the area of high voltage engineering will continue to grow within the electrical energy engineering industry.     

普通高压电源超二代微光像增强器亮度增益温度特性研究

针对匹配普通高压电源的超二代微光像增强器亮度增益在高温条件下大幅下降的问题,根据理论分析搭建了高低温试验平台,并分别对普通高压电源超二代像增强器、像增强管和普通高压电源的高低温特性进行研究。试验结果表明,匹配普通高压电源的超二代像增强器高温（55℃）亮度增益与低温（－55℃）相比衰减约65%;在阴极电压、MCP电压和阳极电压恒定的条件下,像增强管高温亮度增益仅衰减约20%,且主要是由于阴极灵敏度和荧光屏发光效率随温度升高而降低导致的;普通高压电源高温（55℃）与低温（－55℃）相比阴极电压降低约40 V,MCP电压降低约18 V,阳极电压降低约100 V,三者共同作用加剧了普通高压电源超二代像增强器高温亮度增益的衰减。因此,在高温条件下通过软、硬件的方式对电源阴极电压、MCP电压和阳极电压进行补偿是提高普通高压电源超二代微光像增强器高低温亮度增益一致性的有效手段。