一种高效率的适合于低功耗应用的电荷泵电路

设计实现了一种高效率的电荷泵电路。利用电容和晶体管对电荷传输开关进行偏置来消除开关管阈值电压的影响。同时,通过对开关管的的衬底进行动态的偏置使得在电荷传输期间当开关管打开时其阈值电压较低,在开关管关断时其阈值电压较高。该电荷泵电路的效率得到了提高。基于0.18μm,3.3V标准CMOS工艺实现了该电路。在每级电容为0.5pF,时钟频率为780KHz,电源电压为2V的情况下,测得的8级电荷泵的输出电压为9.8V。电荷泵电路和时钟驱动电路从电源处总共消耗了2.9μA的电流。该电荷泵电路适合于低功耗的应用。     

一种基于电荷泵改进型CMOS模拟开关电路

提出了一种基于电荷泵的模拟开关结构.该结构使用电荷泵抬升MOS管的栅电压,从而大大改善开关的导通能力、线性度和动态传输范围.通过仿真验证了开关电路性能,结果表明设计的开关电路在电压0-5V范围内,导通电阻很小且信号损耗很小无失真.因而特别适用于低压系统.     

一种应用于OTP存储器的新型电荷泵的设计

对一次性可编程（OTP）存储器进行编程时需要较大的编程电流,而传统的DICKSON电荷泵电路所提供的编程电流较小,不能满足要求。本文提出了一种适用于OTP存储器的新型电荷泵电路,在3.3V的工作电压下,输出电压7V,内部结点最高电压仅为8.8V,输出上升时间100ns,而且具有较高的电流负载能力,非常适合用于OTP存储器的编程。     

一种应用于EEPROM的片上电荷泵电路设计

设计了一种应用于EEPROM的片内电荷泵电路系统。该电路基于Dickson电荷泵结构,通过使用稳定的参考电压驱动压控振荡电路,从而产生了占空比小于50%的精确时钟,提高了电荷泵升压速度;通过使用调压电路,限制并稳定了输出电压。HSPICE仿真结果显示:在5 V电源电压下,时钟频率高达2.085 MHz。电荷泵仅需要56.256μs就可以输出15.962 V的高压。电荷泵的电压上升时间快,性能优越。     

高性能电荷泵电路设计与HSPICE仿真

电荷泵锁相环具有高速、低功耗、低抖动等特点.电荷泵是锁相环中的关键模块,它实质上是一个开关电流源,需具有精准稳定的恒流源和理想的开关.在模块运行中,一般会出现电荷共享及充放电电流不匹配等现象.通过自举的方法,可以较好地消除电荷共享现象;采用电流跟随电路,可以使充放电电流得到较好匹配.基于2.5 V 0.25 μm CMOS工艺,设计了一个高性能电荷泵.采用Synopsys公司的Hspice仿真软件,对设计的电路进行模拟仿真.结果显示,在1.45 V至2.0 V之间,充放电电流几乎相等.     

应用于Flash存储器的一种高效低纹波电荷泵设计

针对交叉耦合型电荷泵电荷回流的问题,本文提出了一种新型六相位电荷泵结构,电荷泵的主体由3个NMOS管和3个泵电容组成。考虑到时钟驱动能力对电荷泵性能的影响,设计通过增加额外的时钟驱动模块实现四相位到六相位的时钟转换,从而减小电荷泵的上升时间并改善输出电压。此外,电路采用并联双支路结构减小输出电容的充放电时间间隔,以减小输出纹波。基于0.13μm工艺的仿真结果表明,在时钟频率为20MHz,负载电容为50pF,负载电流为300μA的条件下,该电路可以实现3.3V到15V的电压转换,效率可达到67.7%,输出纹波仅为38.5mV。     

带升压结构的双向开关电容电荷泵的设计

介绍了一种结构新颖的升降压式的开关电容电荷泵。着重研究如何缩短该电荷泵的上升时间,使其达到快速启动,通过改变时钟频率并设计升压电路来实现,以满足日益增多的3G手机、PDA、 MP3等便携式设备和高速数据读写场合的要求。在Cadence上采用上海贝岭3微米的DBiCOMS工艺模型进行仿真,结果表明使上升时间缩短33．3％仅需使电路版图面积增加约2．7％。同时针对如何使泵压有稳定输出进行了讨论。     

一种高速低过冲电荷泵电路的设计

为了有效降低传统电荷泵电路的充放电过冲电流,提高电荷泵输出控制电压的稳定性,提出、设计并实现了一种高速低过冲的电荷泵结构,该电路适用于高速锁相环及时钟数据恢复电路.电路在电源电压为1.2 V的0.13 μm CMOS工艺下设计实现,并对版图数据进行了HSPICE模拟,其结果表明,电路在2.5 GHz的速度下能很好的工作,同时电流过冲相比传统电荷泵下降了70%.     

CPLD器件中电荷泵的分析与设计

以CPLD电路中的Dickson电荷泵作为研究和分析的对象,利用CADENCE中的Spectre仿真软件进行电路的仿真验证,分析了电荷泵中输出级负载电容与其电压上升时间的关系,电荷泵产生电压与电荷泵级数、电源电压的关系,三种电荷泵产生电压的区别,及电阻负载对电荷泵上升电压的限制,所得结果对CPLD电路电荷泵设计具有指导意义.     

一种高效率开关频率自适应电荷泵

本文提出了一种新型开关频率自适应电荷泵,它通过自动调节电荷泵开关频率,降低了芯片静态电流.与传统的固定开关频率线性控制电荷泵相比,开关频率自适应电荷泵具有更低的静态电流,更高的转换效率,稍高的输出纹波.特别是在电荷泵工作于轻负载时,其转换效率提升非常显著.理论分析和仿真结果表明在轻负载情况下,开关频率自适应电荷泵的效率比固定开关频率线性控制电荷泵效率提高了10%～40%.     

A dynamic analysis of the Dickson charge pump circuit

Dynamics of the Dickson charge pump circuit are analyzed. The analytical results enable the estimation of the rise time of the output voltage and that of the power consumption during boosting. By using this analysis, the optimum number of stages to minimize the rise time has been estimated as 1.4 N_min, where N_min is the minimum value of the number of stages necessary for a given parameter set of supply voltage, threshold voltage of transfer diodes, and boosted voltage. Moreover, the self-load capacitance of the charge pump, which should be charged up at the same time as the output load capacitance of the charge pump, has been estimated as about one-third of the total charge pump capacitance. As a result, the equivalent circuit of the charge pump has been modified. The analytical results are in good agreement with simulation by the iteration method, typically within 10% for the rise time and within 2% for the power consumption. In the case of a charge pump with MOS transfer transistors, the analytical results of the rise time agree with the SPICE simulation within 10%     

一种PMOS管传输型高效电荷泵电路设计

设计了一种基于传统Dickson结构的PMOS管传输型电荷泵电路。电路通过衬底电位跟随器实现PMOS管传输,避免了传输过程中阈值电压损失;通过电阻分压反馈网络、控制振荡器输出达到稳压的目的;在电荷泵不工作时,各个子电路关断,实现低功耗设计。仿真结果表明,电路效率高,上电时间短,纹波小;采用SMIC 0.18μm工艺流片,电路达到设计要求,输出高压稳定,驱动能力强,在1M EEPROM电路芯片中得到实际应用。     

Analysis and design of power efficient semi-passive RFID tag

The analysis and design of a semi-passive radio frequency identification(RFID) tag is presented.By studying the power transmission link of the backscatter RFID system and exploiting a power conversion efficiency model for a multi-stage AC-DC charge pump,the calculation method for semi-passive tag's read range is proposed.According to different read range limitation factors,an intuitive way to define the specifications of tag's power budget and backscatter modulation index is given.A test chip is implemen...     

A charge pump for driving CMOS active pixel reset

To overcome the limitation of low image signal swing range and long reset time in four Iransistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open performance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage ripple lower than 6 inV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is elIminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 × 10^6 pixels.     

A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.     

Low-voltage charge pump

A low-voltage charge pump, having a symmetrical structure, is proposed. In this charge pump, enhanced switches are used instead of diode-configured MOSTs. The switch-controlling voltage is mutually offered by the two symmetrical branches, which makes the enhanced switches turn on/off alternatively during the designated cycles. Consequently, the voltage drop due to the threshold voltage of MOSTs is eliminated, exhibiting gain in die area, rise time and maximum output voltage.     

一种改进型高性能电流舵电荷泵电路设计

提出一种改进型高性能单端电荷泵电路 ,该电路基于电流舵结构 ,使用运放将偏置电路与充放电电路分开。该电路具有低的输出抖动、宽的电源范围 ,使用级连电流镜像消除过冲注入电流。基于 CMOS0 .3 5工艺 ,用 SPECTRE对该电路进行仿真 ,改进后的电路可消除 1.2 m A的注入电流 ,稳定工作在 2 5 /12 .5 MHz下 ,其最低工作电压为 2 .2 V,静态功耗为 0 .44m A,达到设计目标。     

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.     

电荷泵高端浮动自举式H桥功率驱动电路

提出了一种可以实现极低频甚至是０Ｈｚ下的高压Ｈ桥驱动电路的电荷泵高端浮动自举电路。通过理论分析、仿真和实验。主宰了在保证驱动器的开关速度不变的情况下,该电路能提供稳定物高端浮动电源。同时,对Ｈ桥功率驱动电路中高端浮动自举电路的设计方法也进行了探讨。