端接方式对改善高速电路串扰的分析研究

通过对两条耦合线中的攻击线,采用几种不同的电路端接方式,利用Hyperlynx软件仿真出相应情况下的信号传输波形。通过端接电路在抑制攻击线上反射的同时,减小了受害线上信号的串扰,从而使信号在两条耦合线上的传输质量得到改善。最后进行了多组数据的串扰比较研究,分析了串扰减小的原因。     

考虑串扰影响的时延测试

超深亚微米工艺下，串扰的出现会导致在电路设计验证、测试阶段出现严重的问题。本文介绍了一个基于波形敏化的串扰时延故障测试生成算法。该算法以临界通路上的串扰时延故障为目标故障进行测试产生．大大提高了算法的效率。实验表明，以该算法实现的系统可以在一个可接受的时间内。对一定规模的电路的串扰时延故障进行测试产生。     

高速数字电路PCB中串扰问题的研究与仿真

针对高速数字电路PCB中传输线间串扰的严重性,从精确分析PCB中串扰噪声的角度出发,在传统的双线耦合模型的基础上,采用了一种三线串扰耦合模型。该模型由两条攻击线和一条受害线组成,两条攻击线位于受害线的两侧,线间采取平行耦合的方式。利用信号完整性仿真软件Hyperlynx对受害线上的近端串扰噪声和远端串扰噪声进行了仿真。仿真结果表明,不同的传输模式和传输线类型、信号层与地平面的距离、耦合长度、传输线间距和信号上升/下降沿等因素会对受害线上的近端串扰和远端串扰产生较大的影响。在分析仿真结果的基础上,总结出了高速PCB设计中抑制串扰的有效措施,对高速数字电路设计有一定的指导意义。     

高速电路PCB中串扰的仿真分析与抑制对策

针对串扰在高速电路印刷电路板(PCB)设计中造成严重的信号完整性问题,介绍一种可尽早发现串扰引起的问题的方法。首先利用信号完整性仿真软件HyperLynx,建立两条攻击线夹一条受害线的三线平行耦合串扰仿真模型;然后通过仿真分析传输线平行耦合长度、平行耦合间距、传输线类型、信号层与地平面层之间的介质厚度等因素对串扰噪声的影响;最后综合这些影响因素,并根据PCB设计顺序,给出抑制串扰的详细措施。实践表明,这些措施对高速PCB的设计,具有实用、可靠和提高设计效率的意义。     

高精度光纤陀螺检测电路串扰自检测研究

光纤陀螺检测电路应用过程中,受到自检测方案的影响,导致串扰故障检测所需测试矢量较多。因此,提出高精度光纤陀螺检测电路串扰自检测研究。分析光纤陀螺数字闭环检测原理,并提取检测电路串扰特征。根据闭环电路的连续信号微分方程,计算等效模拟输入转速。结合数字阶梯波算法,设计电路串扰检测方案。再计算地球自转角速率的分量测量死区,得到电路串扰测量结果。仿真结果表明：所提出的串扰自检测方法,与嵌入式“反射器”的新型谐振陀螺仪和多导体传输线串扰不确定性问题的计算方法相比,当串扰故障覆盖率为80%,本文方法的矢量数量为46个,降低了自测试所需的成本。     

考虑串扰效应的性能驱动全局布线器研究

提出了利用符号化矩计算模型进行性能驱动的多级布线方法.通过在模式布线阶段利用符号化矩计算模型,快速得到电路的高阶矩,并根据计算结果,采用合理的代价函数对时延串扰等性能指标进行预估,进而指导布线.实验结果显示,该算法在串扰优化方面得到较大的提高,布线结果兼顾了时延优化和信号波形质量优化.     

一种基于神经网络的组合电路测试生成算法

介绍了一种基于神经网络的组合电路测试生成算法。利用Hopfield神经网络模型将组合电路表示成对应的神经网络,通过建立被测电路的约束网络,构造神经网络的能量函数,使组合电路的测试矢量对应神经网络能量函数的最小值点,使得测试生成问题数学化,并使用遗传算法求解能量函数的最小值点得到故障电路的测试矢量。通过在一些标准电路的实验表明,该测试生成算法有效可行。     

基于分组网络结构NoC的BIST串扰测试方法

针对大规模NoC芯片设计中BIST测试时间长和消耗面积大的问题,提出一种测试NoC内switch间互连线串扰的BIST方法。对于互连线工作在1 GHz以下的大规模NoC,电容耦合是影响串扰的主要因素。通过并行测试结构,同时对几条受害线进行测试,有效减小了测试时间和电路面积。从理论角度对所提方法的测试时间和功率损耗进行了分析,以3×3 mesh结构的NoC为例,验证了所提方案和理论分析的正确性。     

小型化高精度光纤陀螺的检测电路串扰自检测

在高精度光纤陀螺小型化过程中,检测电路串扰问题越发严重,在复杂应用环境下难以采用基于转台的传统方法测试光纤陀螺串扰在输出中的表现。基于此,提出一种基于施加模拟转速阶梯波的测试方法。该方法使用专用电路生成台阶高度人为可控的阶梯波,利用加法电路将其与闭环阶梯波叠加接入Y波导,通过测试陀螺响应,可确定串扰大小。对该方法进行相关实验验证,实验结果表明:该方法能在不依赖于转台的条件下实现光纤陀螺检测电路串扰的自检测,提升了应用系统的设计与测试效率。     

微米级平行互连线的测试结构设计

研究分析无串扰传输理想模型的条件,根据高速高密度电路板中微米级、亚毫米级互连线电磁串扰特性研究需要,首次提出微米级平行互连线的测试结构设计。经射频电路理论分析推导了测试结构对系统串扰没有影响。构建了有、无测试结构的微米级平行互连线物理模型,仿真分析后,加工制作有测试结构的微米级平行互连线电路板。研究结果表明,当数字基带信号传输频率在0~3 GHz 范围时,无测试结构仿真电路模型、有测试结构仿真电路模型、有测试结构的实验电路板,三者串扰特性吻合;微米级平行互连线的测试结构设计合理,具有工程参 考价值。     

Delay calculation capturing crosstalk effects due to coupling capacitors

A driver model to calculate gate and interconnect delays accurately for a chip with coupling capacitors is presented. The crosstalk effects between simultaneously switching victim and aggressors are effectively captured by iteratively solving an N-port RC network. The algorithm was implemented in a delay calculation tool called XINT and its accuracy demonstrated for industrial designs.     

A multiline model for time-efficient estimation of crosstalk

This work proposes a novel and accurate crosstalk noise estimation method in the presence of multiple RC lines for use in design automation tools. Using the realistic exponential waveform and a reduced transfer function, the proposed model presents a complete multiline noise model by representing active and passive aggressors simultaneously on the victim line. In the model, active aggressors are easily represented by current sources and passive aggressors are accurately modeled as equivalent capacitances to victim. Each current source representing an active aggressor carries the same accuracy as the 2-π representation. Equivalent capacitances for passive aggressors, on the other hand, consider resistive shielding effect and the realistic exponential aggressor waveform. This approach allows one to obtain a general noise model that considers the effect of many active and passive aggressors and general formulas derived can easily be applied to real cases. Noise peak and width expressions are derived and results are in good agreement with HSPICE results. Results show that average error for noise peak is 4.3% and for the width is 6.9% while allowing for very fast analysis.     

Efficient Path Delay Test Generation for Custom Designs

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.     

Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis

Three-dimensional (3D) integration is a key technology for systems whose performance and power requirements cannot be achieved by traditional silicon technologies. 3D chips consist of two or more stacked silicon dies connected by short inter-die wires called Thru-Silicon-Vias (TSVs). Despite its potential, the poor reliability and yield, thermal management and testing issues remain major challenges of 3D integration. We address the TSV interconnect test challenge of 3D chips by using Interconnect Built-In Self-Test (IBIST) techniques. The proposed test strategy must sensitize structural faults like opens and shorts, and delay faults due to crosstalk. A possible approach is the well-known Maximum Aggressor Fault (MAF) model. Unfortunately, this model is too conservative and it leads to long test sequences and non-negligible hardware costs. Therefore, we present an alternative solution: the K^th-Aggressor Fault (KAF) model. In our model, aggressors of victim wires are neighboring wires within an optimized distance order K. The aggressor order K is technology-dependent and is determined such that the test times are minimal and the fault coverage is maximal. KAF-based IBIST implementation targeting TSV tests occupies three times less area than similar MAF-/marching-based implementations. We also propose a reconfigurable KAF-based IBIST implementation where tests can be performed using different aggressor orders K. Although the reconfigurable IBIST area is significant, interconnect tests during system lifetime can be performed using lower aggressor orders, reducing test duration and improving TSV availability.     

A rated-clock test method for path delay faults

Current test generation algorithms for path delay faults assume a variable-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan sequential circuit testing is impractical. A rated-clock path delay simulator shows a large drop in coverage for vectors obtained from existing test generators that assume a variable clock. A new test generation algorithm provides valid tests for uniform rated-clock test application. In this algorithm, signals are represented for three-vector sequences. The test generation procedure activates a target path from input to output using the three-vector algebra. For an effective backward justification, we derive an optimal 41-valued algebra. This is the first time, rated-clock tests for large circuits are obtained. Results for ISCAS-89 benchmarks show that rated-clock tests cover some longest, or close to longest, paths     

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing

In this study, a novel path clustering technique for adaptive path delay testing, where the test paths are altered according to the extracted device parameters, is proposed. The proposed algorithm is based on the k-means++ algorithm. By considering the probability function of the die-to-die systematic process variation, the proposed algorithm clusters path sets to minimize the total number of test paths. A figure of merit for clustering, which represents the expected number of test paths, is also proposed for quantitatively evaluating path clustering under different conditions. The proposed clustering method is evaluated numerically by applying it to the OpenCores benchmark circuit. Using our clustering technique, the average number of test paths in the adaptive test is reduced to less than 92 % compared with those in the conventional test. In addition, adaptive testing using the proposed technique can reduce the test patterns by 94.26 % while retaining the test quality.     

A heuristic multicast algorithm to support QoS group communications in heterogeneous network

This paper examines the problem of quality-of-service group communications in a heterogeneous network, which consists of multiple mobile ad hoc networks attached to the backbone Internet. A heuristic multicast algorithm named delay and delay variation multicast algorithm (DDVMA) is proposed. DDVMA is designed for solving the delay- and delay-variation-bounded multicast tree problem, which has been proved to be NP-complete. It can find a multicast tree satisfying the multicast end-to-end delay constraint and minimizing the multicast delay variation. Two concepts, which can help the DDVMA achieve better performance in terms of multicast delay variation than the delay and delay variation constraint algorithm that is known to be the most efficient so far, are proposed, namely, 1) the proprietary second shortest path and 2) the partially proprietary second shortest path. An analysis is given to show the correctness of DDVMA, and simulations are conducted to demonstrate the performance improvement of DDVMA in terms of multicast delay variation. It is also shown that the strategy employed by DDVMA is also applicable to handling the mobility of mobile hosts in a heterogeneous network.     

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to detect small delay defects and to verify the correct temporal behavior of a circuit. In this article, MONSOON, an efficient SAT-based approach for generating non-robust and robust test patterns for path delay faults is presented. MONSOON handles tri-state elements and environmental constraints occurring in industrial practice using multiple-valued logics. Structural techniques increase the efficiency of the algorithm. A comparison with a state-of-the-art approach shows a significant speed-up. Experimental results for large industrial circuits demonstrates the feasibility and robustness of MONSOON.     

Implementation Method of Cutting Simulation Based on Transient Display and Delay Adjustment Strategy

In the light of the problems that exist in the current cutting algorithms: first, the number of tetrahedron elements increases as the cutting goes on, which leads to the decrease of the algorithm efficiency. Second, the topology structure is constantly updated during the cutting process, which leads to the stutter phenomenon in cutting display. In this paper, a cutting simulation implementation method based on transient display and delay adjustment strategy is proposed. Firstly, the feature points in the original path are screened by the feature criterion function, and the feature path is established. Then, by using the concept of minimum sum of square defined in this paper, the optimal path of the separation is found with the help of feature path points, and the pseudo effect of cutting is directly displayed by designing the transient display module. The delay adjustment is carried out in the cutting gap, and the topology separation in the delay adjustment is implemented by the node offset spread algorithm and the duplicate removal process with timeliness. Finally, the advantages and feasibility of the cutting algorithm proposed in this paper are verified by practical tests. The test results show that the transient display algorithm proposed in this paper takes about 20 ms. With the number of triangular patches increasing, the growth rate of transient display time remains low. The cutting simulation is implemented by using transient display and delay adjustment strategy, which greatly improves the simulation efficiency.     

Highly testable design of BiCMOS logic circuits

Most of the work reported in the literature to date on the testability of BiCMOS circuits has concentrated on fault characterization and the need for a suitable testing method that can address the peculiarities of BiCMOS circuits. The problem of adequately testing large BiCMOS logic networks remains open and complex. In this paper, we introduce a new design for testability technique for BiCMOS logic gates that results in highly testable BiCMOS logic circuits. The proposed design incorporates two features: a test charge/discharge path and built-in current sensing (BICS). The test charge/discharge path is activated only during testing and facilitates the testing of stuck-open faults using single test vectors. BICS facilitates testing of faults that cause excessive IDDQ. HSPICE simulation results show that the proposed design can detect stuck-open faults at a test speed of 10 MHz. Faults causing excessive IDDQ are detected by BICS with a detection time of 1 ns and a settling time of 2 ns. Impact of the proposed design on normal operation is minimal. The increase in propagation delay in normal operation is less than 3%. This compares very favorably with CMOS BICS reported in the literature, where the propagation delay increase was 20%, 14.4% respectively. The increase in the area is less than 15%