CdTe solar cell in a novel configuration

Polycrystalline thin‐film CdTe/CdS solar cells have been developed in a configuration in which a transparent conducting layer of indium tin oxide (ITO) has been used for the first time as a back electrical contact on p‐CdTe. Solar cells of 7·9% efficiency were developed on SnO_x:F‐coated glass substrates with a low‐temperature (<450°C) high‐vacuum evaporation method. After the CdCl₂ annealing treatment of the CdTe/CdS stack, a bromine methanol solution was used for etching the CdTe surface prior to the ITO deposition. The unique features of this solar cell with both front and back contacts being transparent and conducting are that the cell can be illuminated from either or both sides simultaneously like a ‘bi‐facial’ cell, and it can be used in tandem solar cells. The solar cells with transparent conducting oxide back contact show long‐term stable performance under accelerated test conditions. Copyright © 2004 John Wiley & Sons, Ltd.     

Influence of Thiol Self‐Assembled Monolayer Processing on Bottom‐Contact Thin‐Film Transistors Based on n‐Type Organic Semiconductors

The performance of bottom‐contact thin‐film transistor (TFT) structures lags behind that of top‐contact structures owing to the far greater contact resistance. The major sources of the contact resistance in bottom‐contact TFTs are believed to reflect a combination of non‐optimal semiconductor growth morphology on the metallic contact surface and the limited available charge injection area versus top‐contact geometries. As a part of an effort to understand the sources of high charge injection barriers in n‐channel TFTs, the influence of thiol metal contact treatment on the molecular‐level structures of such interfaces is investigated using hexamethyldisilazane (HMDS)‐treated SiO₂ gate dielectrics. The focus is on the self‐assembled monolayer (SAM) contact surface treatment methods for bottom‐contact TFTs based on two archetypical n‐type semiconductors, α,ω‐diperfluorohexylquarterthiophene (DFH‐4T) and N,N′bis(n‐octyl)‐dicyanoperylene‐3,4:9,10‐bis(dicarboximide) (PDI‐8CN₂). TFT performance can be greatly enhanced, to the level of the top contact device performance in terms of mobility, on/off ratio, and contact resistance. To analyze the molecular‐level film structural changes arising from the contact surface treatment, surface morphologies are characterized by atomic force microscopy (AFM) and scanning tunneling microscopy (STM). The high‐resolution STM images show that the growth orientation of the semiconductor molecules at the gold/SAM/semiconductor interface preserves the molecular long axis orientation along the substrate normal. As a result, the film microstructure is well‐organized for charge transport in the interfacial region.     

Novel Cu Nanowires/Graphene as the Back Contact for CdTe Solar Cells

Cu‐nanowire‐doped graphene (Cu NWs/graphene) is successfully incorporated as the back contact in thin‐film CdTe solar cells. 1D, single‐crystal Cu nanowires (NWs) are prepared by a hydrothermal method at 160 °C and 3D, highly crystalline graphene is obtained by ambient‐pressure CVD at 1000 °C. The Cu NWs/graphene back contact is obtained from fully mixing the Cu nanowires and graphene with poly(vinylidene fluoride) (PVDF) and N‐methyl pyrrolidinone (NMP), and then annealing at 185 °C for solidification. The back contact possesses a high electrical conductivity of 16.7 S cm^?1 and a carrier mobility of 16.2 cm² V^?1 s^?1. The efficiency of solar cells with Cu NWs/graphene achieved is up to 12.1%, higher than that of cells with traditional back contacts using Cu‐particle‐doped graphite (10.5%) or Cu thin films (9.1%). This indicates that the Cu NWs/graphene back contact improves the hole collection ability of CdTe cells due to the percolating network, with the super‐high aspect ratio of the Cu nanowires offering enormous electrical transport routes to connect the individual graphene sheets. The cells with Cu NWs/graphene also exhibit an excellent thermal stability, because they can supply an active Cu diffusion source to form an stable intermediate layer of CuTe between the CdTe layer and the back contact.     

CdTe/CdS thin film solar cells grown in substrate configuration

The ability to grow efficient CdTe/CdS solar cells in substrate configuration would not only allow for the use of non‐transparent and flexible substrates but also enable a better control of junction formation. Yet, the problems of barrier formation at the back contact as well as the formation of a p–n junction with reduced recombination losses have to be solved. In this work, CdTe/CdS solar cells in substrate configuration were developed, and the results on different combinations of back contact materials are presented. The Cu content in the electrical back contact was found to be a crucial parameter for the optimal CdCl₂‐treatment procedure. For Cu‐free cells, two activation treatments were applied, whereas Cu‐containing cells were only treated once after the CdTe deposition. A recrystallization behavior of the CdTe layer upon its activation similar to superstrate configuration was found; however, no CdTe–CdS intermixing could be observed when the layers were treated consecutively. Remarkably high V_OC and fill factor of 768 mV and 68.6%, respectively, were achieved using a combination of MoO₃, Te, and Cu as back contact buffer layer resulting in 11.3% conversion efficiency. With a Cu‐free MoO₃/Te buffer material, a V_OC of 733 mV, a fill factor of 62.3%, and an efficiency of 10.0% were obtained. Copyright © 2012 John Wiley & Sons, Ltd.     

Numerical simulations of buried emitter back‐junction solar cells

We recently introduced the buried emitter back‐junction solar cell, featuring large area fractions of overlap between n⁺‐type and p⁺‐type regions at the rear side of the device. In this paper we analyse the performance of the buried emitter solar cell (BESC) and its generalisations by one‐dimensional device simulations and analytical model calculations. A key finding is that the generalised versions of the BESC structure allows achieving very high efficiencies by passivating virtually the entire surface of p‐type emitters by an oxidised n‐type surface layer. A disadvantage of this type of full‐area emitter passivation in the generalised back‐junction BESC is the need for an insulating layer between the metallisation of the emitter and the contact to the base, which is technologically difficult to achieve. Copyright © 2009 John Wiley & Sons, Ltd.     

Influence of the layer parameters on the performance of the CdTe solar cells

Influence of the layer parameters on the performances of the CdTe solar cells is analyzed by SCAPS-1D. The ZnO:Al film shows a high efficiency than SnO2:F. Moreover, the thinner window layer and lower defect density of CdS films are the factor in the enhancement of the short-circuit current density. As well, to increase the open-circuit voltage, the responsible factors are low defect density of the absorbing layer CdTe and high metal work function. For the low cost of cell production, ultrathin film CdTe cells are used with a back surface field (BSF) between CdTe and back contact, such as PbTe. Further, the simulation results show that the conversion efficiency of 19.28% can be obtained for the cell with 1-μm-thick CdTe, 0.1-μm-thick PbTe and 30-nm-thick CdS.     

13·9%‐efficient CdTe polycrystalline thin‐film solar cells with an infrared transmission of ∼50%

To fabricate a high‐efficiency polycrystalline thin‐film tandem cell, the most critical work is to make a high‐efficiency top cell ( > 15%) with high bandgap (E_g = 1·5–1·8 eV) and high transmission (T > 70%) in the near‐infrared (NIR) wavelength region. The CdTe cell is one of the candidates for the top cell, because CdTe state‐of‐the‐art single‐junction devices with efficiencies of more than 16% are available, although its bandgap (1·48 eV) is slightly lower for a top cell in a current‐matched dual‐junction device. In this paper, we focus on the development of a: (1) thin, low‐bandgap Cu_xTe transparent back‐contact; and (2) modified CdTe device structure, including three novel materials: cadmium stannate transparent conducting oxide (TCO), ZnSnO_x buffer layer, and nanocrystalline CdS:O window layer developed at NREL, as well as the high‐quality CdTe film, to improve transmission in the NIR region while maintaining high device efficiency. We have achieved an NREL‐confirmed 13·9%‐efficient CdTe transparent solar cell with an infrared transmission of ∼50% and a CdTe/CIS polycrystalline mechanically stacked thin‐film tandem cell with an NREL‐confirmed efficiency of 15·3%. Copyright © 2005 John Wiley & Sons, Ltd.     

Focussed ion beam and field emission gun–scanning electron microscopy for the investigation of voiding and interface phenomena in thin‐film solar cells

The use of focussed ion beam milling combined with high resolution scanning electron microscopy analysis as a characterisation tool for thin‐film photovoltaics is reported. CdTe solar cell cross sections are examined in high detail with as‐grown and CdCl₂‐treated devices being compared. Observed changes in microstructure of the thin‐film layers are related to the device performance. The CdCl₂ treatment is shown to cause a reduction in the CdTe defect density at regions close to the interface and induce recrystallization of the CdS layer. Furthermore, the focussed ion beam technique is shown to reveal voids formed within the device's thin‐film layers at various processing stages that have not been previously observed in working cell structures. The back‐contacting Te‐rich layer resulting from nitric–phosphoric acid etching is also observed, with the etched layer being seen to propagate down the CdTe grain boundaries. Copyright © 2011 John Wiley & Sons, Ltd.     

Modeling of temperature profile,thermal runaway and hot spot in thin film solar cells

Hot spot and thermal runaway are serious phenomena leading to the degradation of CdTe thin film solar cells. Here, we show that these issues are well related to temperature variation in the device structures mostly because of current flowing across transparent conducting oxide (TCO) layer or back contact of a CdTe device structure: glass/TCO/CdS/CdTe/graphene. Graphene nanolayer was chosen as the back contact because of its high thermal conductivity. We present a modeling of the temperature profile in CdTe thin film devices considering both uniform and nonuniform temperature distribution and current flowing across TCO layer. Temperature profile for hot spots at the edges of devices are modeled and compared to literature reports of both modelled and measured data. The model is based on the heat transfer equation (which uses thermal resistances) and in particular accounts for convection and conduction resistances by means of their ratio, the Biot number – a factor that could be optimized in the design of photovoltaic devices. Profiles were modelled taking into account both uniform and non-uniform temperature profiles for the glass, and currents flowing though the TCO. It is shown that the current flowing across the TCO layer can contribute to thermal runaway and its spreading to neighbouring areas. Overall the modelling data suggests that thin film solar devices could be designed to minimise hot spot runaway issues by taking into account the thickness and temperature dependence of the layers thermal conductivity, convection and conduction resistances. This can be extended to other solar cell structures or large scale modules.     

Experimental and simulated analysis of front versus all‐back‐contact silicon heterojunction solar cells: effect of interface and doped a‐Si:H layer defects

Front silicon heterojunction and interdigitated all‐back‐contact silicon heterojunction (IBC‐SHJ) solar cells have the potential for high efficiency and low cost because of their good surface passivation, heterojunction contacts, and low temperature fabrication processes. The performance of both heterojunction device structures depends on the interface between the crystalline silicon (c‐Si) and intrinsic amorphous silicon [(i)a‐Si:H] layer, and the defects in doped a‐Si:H emitter or base contact layers. In this paper, effective minority carrier lifetimes of c‐Si using symmetric passivation structures were measured and analyzed using an extended Shockley–Read–Hall formalism to determine the input interface parameters needed for a successful 2D simulation of fabricated baseline solar cells. Subsequently, the performance of front silicon heterojunction and IBC‐SHJ devices was simulated to determine the influence of defects at the (i)a‐Si:H/c‐Si interface and in the doped a‐Si:H layers. For the baseline device parameters, the difference between the two device configurations is caused by the emitter/base contact gap recombination and the back surface geometry of IBC‐SHJ solar cell. This work provides a guide to the optimization of both types of SHJ device performance, predicting an IBC‐SHJ solar cell efficiency of 25% for realistic material parameters. Copyright © 2013 John Wiley & Sons, Ltd.     

Progression of metalorganic chemical vapour‐deposited CdTe thin‐film PV devices towards modules

This paper reports important developments achieved with CdTe thin‐film photovoltaic devices produced using metalorganic chemical vapour deposition at atmospheric pressure. In particular, attention was paid to understand the enhancements in solar cell conversion efficiency, to develop the cell design, and assess scalability towards modules. Improvements in the device performance were achieved by optimising the high‐transparency window layer (Cd_0.3Zn_0.7S) and a device‐activation anneal. These increased the fill factor and open‐circuit voltage to 77 ± 1% and 785 ± 7 mV, respectively, compared with 69 ± 3% and 710 ± 10 mV for previous baseline devices with no anneal and thicker Cd_0.3Zn_0.7S. The enhancement in these parameters is associated with the two fold to three fold increase in the net acceptor density of CdTe upon air annealing and a decrease in the back contact barrier height from 0.24 ± 0.01 to 0.16 ± 0.02 eV. The optimum thickness of the window layer for maximum photocurrent was 150 nm. The cell size was scaled from 0.25 to 2 cm² in order to assess its impact on the device series resistance and fill factor. Finally, micro‐module devices utilising series‐connected 2‐cm² sub‐cells were fabricated using a combination of laser and mechanical scribing techniques. An initial module‐to‐cell efficiency ratio of 0.9 was demonstrated for a six‐cell module with the use of the improved device structure and processing. Prospects for CdTe photovoltaic modules grown by metalorganic chemical vapour deposition are commented on. Copyright © 2015 John Wiley & Sons, Ltd.     

Factors Affecting the Stability of CdTe/CdS Solar Cells Deduced from Stress Tests at Elevated Temperature

CdTe/CdS solar cells were subjected to heat stress at 200 °C in the dark under different environments (in N₂ and in air), and under illumination (in N₂). We postulate that two independent mechanisms can explain degradation phenomena in these cells: i) Excessive Cu doping of CdS: Accumulation of Cu in the CdS with stress, in the presence of Cl, will increase the photoconductivity of CdS. With limited amounts of Cu in CdS, this does NOT affect the photovoltaic behavior, but explains the crossover of light/dark current–voltage (J–V) curves. Overdoping of CdS with Cu can be detrimental to cell performance by creating deep acceptor states, acting as recombination centers, and compensating donor states. Under illumination, the barrier to Cu cations at the cell junction is reduced, and, therefore, Cu accumulation in the CdS is enhanced. Recovery of light‐stress induced degradation in CdTe/CdS cells in the dark is explained by dissociation of the acceptor defects. ii) Back contact barrier: Oxidation of the CdTe back surface in O₂/H₂O‐containing environment to form an insulating oxide results in a back‐contact barrier. This barrier is expressed by a rollover in the J–V curve. Humidity is an important factor in air‐induced degradation, as it accelerates the oxide formation. Heat treatment in the dark in inert atmosphere can stabilize the cells against certain causes of degradation, by completing the back contact anneal.     

Stable CdTe thin film solar cells with a MoOx back‐contact buffer layer

MoO_x thin films were employed as a buffer layer in the back contact of CdTe solar cells. A monograined CdS layer was employed as the window layer to reduce light absorption. The insertion of a MoO_x buffer layer in the back contact greatly reduced the Schottky barrier leading to increased fill factor and open‐circuit voltage. A CdTe solar cell, with an efficiency as high as 14.2%, was fabricated. The use of a MoO_x buffer layer made it possible to fabricate high‐efficient CdTe solar cell with much less Cu in the back contact, thus greatly enhancing the cell stability. Copyright © 2015 John Wiley & Sons, Ltd.     

20.7% efficient ion‐implanted large area n‐type front junction silicon solar cells with rear point contacts formed by laser opening and physical vapor deposition

In this work, we report on ion‐implanted, high‐efficiency n‐type silicon solar cells fabricated on large area pseudosquare Czochralski wafers. The sputtering of aluminum (Al) via physical vapor deposition (PVD) in combination with a laser‐patterned dielectric stack was used on the rear side to produce front junction cells with an implanted boron emitter and a phosphorus back surface field. Front and back surface passivation was achieved by thin thermally grown oxide during the implant anneal. Both front and back oxides were capped with SiN_x, followed by screen‐printed metal grid formation on the front side. An ultraviolet laser was used to selectively ablate the SiO₂/SiN_x passivation stack on the back to form the pattern for metal–Si contact. The laser pulse energy had to be optimized to fully open the SiO₂/SiN_x passivation layers, without inducing appreciable damage or defects on the surface of the n⁺ back surface field layer. It was also found that a low temperature annealing for less than 3 min after PVD Al provided an excellent charge collecting contact on the back. In order to obtain high fill factor of ~80%, an in situ plasma etching in an inert ambient prior to PVD was found to be essential for etching the native oxide formed in the rear vias during the front contact firing. Finally, through optimization of the size and pitch of the rear point contacts, an efficiency of 20.7% was achieved for the large area n‐type passivated emitter, rear totally diffused cell. Copyright © 2014 John Wiley & Sons, Ltd.     

Evaporated Te on CdTe: A vacuum-compatible approach to making back contact to CdTe solar cell devices

A commonly used process for forming low-resistance contacts to thin-film p-type CdTe involves the formation of a Te layer by etching the CdTe film in a concentrated mixture of nitric and phosphoric acids. The authors compare evaporated Te back contacts with ‘control’ back contacts formed by the usual etching process, and demonstrate that evaporating Te onto a CdTe thin film is a viable process for forming a low-resistance contact. The best efficiency achieved for a CdTe solar cell made with an evaporated Te back contact is 12.1%, whereas the efficiency of the device made with the control back contact was 11.9%. The evaporation process offers numerous advantages over acid etching, most notably vacuum compatibility amenable to large-scale production of CdTe solar cell modules.     

Application of copper thiocyanate for high open‐circuit voltages of CdTe solar cells

Copper thiocyanate (CuSCN) has proven to be a low‐cost, efficient hole‐transporting material for the emerging organic–inorganic perovskite solar cells. Herein, we report that CuSCN can also be applied to CdTe thin‐film solar cells to achieve high open‐circuit voltages (V_OCs). By optimizing the thickness of the thermally evaporated CuSCN films, CdTe cells fabricated by close space sublimation in the superstrate configuration have achieved V_OCs as high as 872 mV, which is about 20–25 mV higher than the highest V_OC for the reference cells using the standard Cu/Au back contacts. CuSCN is a wide bandgap p‐type conductor with a conduction band higher than that of CdTe, leading to a conduction band offset that reflects electrons in CdTe, partially explaining the improved V_OCs. However, due to the low conductivity of CuSCN, CdTe cells using CuSCN/Au back contacts exhibited slightly lower fill factors than the cells using Cu/Au back contacts. With optimized CdS:O window layers, the power conversion efficiency of the best CdTe cell, using CuSCN/Au back contact, is 14.7%: slightly lower than that of the best cell (15.2%) using Cu/Au back contact. Copyright © 2015 John Wiley & Sons, Ltd.     

Study of Back Contacts for CdTe Solar Cells

ZnTe/ZnTe:Cu layer is used as a complex back contact.The parmeters of CdTe solar cells with and without the complex back contacts are compared.The effects of un-doped layer thickness,doped concentration and post-deposition annealing temperature of the complex layer on solar cells preformance are investigated.The results show that ZnTe/ZnTe:Cu layer can improve back contacts and largely increase the conversion efficiency of CdTe solar cells.Un-doped layer and post-deposition annealing of high temperature can increase open voltage.Using the complex back contact,a small CdTe cell with fill factor of 73.14% and conversion efficiency of 12.93% is obtained.     

Enhanced lateral current transport via the front N+ diffused layer of n‐type high‐efficiency back‐junction back‐contact silicon solar cells

N‐type back‐contact back‐junction solar cells were processed with the use of industrially relevant structuring technologies such as screen‐printing and laser processing. Application of the low‐cost structuring technologies in the processing of the high‐efficiency back‐contact back‐junction silicon solar cells results in a drastic increase of the pitch on the rear cell side. The pitch in the range of millimetres leads to a significant increase of the lateral base resistance. The application of a phosphorus doped front surface field (FSF) significantly reduces the lateral base resistance losses. This additional function of the phosphorus doped FSF in reducing the lateral resistance losses was investigated experimentally and by two‐dimensional device simulations. Enhanced lateral majority carrier's current transport in the front n⁺ diffused layer is a function of the pitch and the base resistivity. Experimental data show that the application of a FSF reduces the total series resistance of the measured cells with 3.5 mm pitch by 0.1 Ω cm² for the 1 Ω cm base resistivity and 1.3 Ω cm² for the 8 Ω cm base resistivity. Two‐dimensional simulations of the electron current transport show that the electron current density in the front n⁺ diffused layer is around two orders of magnitude higher than in the base of the solar cell. The best efficiency of 21.3% was obtained for the solar cell with a 1 Ω cm specific base resistivity and a front surface field with sheet resistance of 148 Ω/sq. Copyright © 2008 John Wiley & Sons, Ltd.     

Impact of Materials versus Geometric Parameters on the Contact Resistance in Organic Thin‐Film Transistors

The contact resistance is known to severely hamper the performance of organic thin‐film transistors, especially when dealing with large injection barriers, high mobility organic semiconductors, or short channel lengths. Here, the relative significance of how it is affected by materials‐parameters (mobility and interfacial level‐offsets) and geometric factors (bottom‐contact vs top‐contact geometries) is assessed. This is done using drift‐diffusion‐based simulations on idealized device structures aiming at a characterization of the “intrinsic” situation in the absence of traps, differences in the film morphology, or metal‐atoms diffusing into the organic semiconductor. It is found that, in contrast to common wisdom, in such a situation the top‐contact devices do not always outperform the bottom‐contact ones. In fact, the observed ratio between the contact resistances of the two device structures changes by up to two orders of magnitude depending on the assumed materials parameters. The contact resistance is also shown to be strongly dependent on the hole mobility in the organic semiconductor and influenced by the chosen point of operation of the device.