Fabrication of nanosized molecular array device and logic gate using dimethyl-phenylethynyl thiol

We fabricated an array of molecular devices with a simple vertical metal-molecule-metal (MMM) junction. The nano via holes are formed in SiNx or SiO2 layer by RIE to contain the molecules inside. Finally, the top Ti/Au contact has been deposited by e-beam evaporation with cooling stage. By using self-assembly process, the organic molecules dissolved in dry and oxygen-free THF are inserted to the nanopore array device for 24 hours. We used the newly synthesized compound 4-[4-(3,5-Dimethyl-phenylethynyl)-3-nitro-phenylethynyl]-benzenethiol (DN), which is designed for adding two methyl groups at 3,5 position of phenylethynyl group of Tour's compound (4-(2-Nitro-4-phenylethynyl-phenylethyyl)-benzenethiol). The molecular devices produced the diode-like I-V characteristics and were implemented to logic gate with 3 x 3 array devices containing the DN molecule.     

Electrically defined ferromagnetic nanodots

While ferromagnetic nanodots are being widely studied from fundamental as well as application points of views, so far all the dots have been physically defined; once made, one cannot change their dimension or size. We show that ferromagnetic nanodots can be electrically defined. To realize this, we utilize an electric field to modulate the in-plane distribution of carriers in a ferromagnetic semiconductor (Ga,Mn)As film with a meshed gate structure having a large number of nanoscaled windows.     

Novel all-optical logic gate using an add/drop filter and intensity switch

A novel design of all-optical logic device is proposed. An all-optical logic device system composes of an optical intensity switch and add/drop filter. The intensity switch is formed to switch signal by using the relationship between refraction angle and signal intensity. In operation, two input signals are coupled into one with some coupling loss and attenuation, in which the combination of add/drop with intensity switch produces the optical logic gate. The advantage is that the proposed device can operate the high speed logic function. Moreover, it uses low power consumption. Furthermore, by using the extremely small component, this design can be put into a single chip. Finally, we have successfully produced the all-optical logic gate that can generate the accurate AND and NOT operation results.     

Optical bistability in vertical-cavity semiconductor optical amplifiers

We present an overview of the properties and applications of optical bistability in vertical-cavity semiconductor optical amplifiers (VCSOAs). The basic physics and analytical models of this optical nonlinearity are discussed. Experimental results obtained from a VCSOA operated in the 850 nm wavelength region are presented. Counterclockwise hysteresis loops are obtained over a range of initial phase detuning and bias currents. One hysteresis loop is observed experimentally with an input power as low as 2 muW when the device is biased at 98% of its lasing threshold. Numerical simulations based on the Fabry-Perot resonator model and rate equations we developed show good agreement with our experimental observations. In addition, a low input intensity high contrast (10:1) optical and gate and 2R regeneration are demonstrated. We believe that bistable VCSOAs can significantly advance the prospect of a dense two-dimensional array of low-switching-intensity all-optical logic and memory elements.     

Nonvolatile memory characteristics of solution-processed oxide thin-film transistors using Ag nanoparticles

We developed a nonvolatile memory device based on a solution-processed oxide thin-film transistor (TFT) with Ag nanoparticles (NPs) as the charge trapping layer. We fabricated the device using a soluble MgInZnO active channel on a SiO₂ gate dielectric, Ag NPs as a charge trapping site at the gate insulator-channel interface, and Al for source and drain electrodes.The transfer characteristics of the device showed a high level of clockwise hysteresis that can be used to demonstrate its memory function, due to electron trapping in the Ag NPs charge trapping layer. A large memory window (?V_th) was observed with a forward and backward gate voltage sweep, and this memory window was increased in size by increasing the gate voltage sweep. These results show the potential application of memory on displays and disposable electronics.     

Constructing Online Testable Circuits Using Reversible Logic

With the advent of nanometer technology, circuits are more prone to transient faults that can occur during its operation. Of the different types of transient faults reported in the literature, the single-event upset (SEU) is prominent. Traditional techniques such as triple-modular redundancy (TMR) consume large area and power. Reversible logic has been gaining interest in the recent past due to its less heat dissipation characteristics. This paper proposes the following: 1) a novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature; (2) a reversible gate that can mimic the functionality of a lookup table (LUT) that can be used to construct a reversible field-programmable gate array (FPGA); and (3) automatic conversion of any given reversible circuit into an online testable circuit that can detect online any single-bit errors, including soft errors in the logic blocks, using theoretically proved minimum garbage, which is significantly lesser than the best reported in the literature.      

Tunable Tribotronic Dual‐Gate Logic Devices Based on 2D MoS2 and Black Phosphorus

With the Moore's law hitting the bottleneck of scaling‐down in size (below 10 nm), personalized and multifunctional electronics with an integration of 2D materials and self‐powering technology emerge as a new direction of scientific research. Here, a tunable tribotronic dual‐gate logic device based on a MoS₂ field‐effect transistor (FET), a black phosphorus FET and a sliding mode triboelectric nanogenerator (TENG) is reported. The triboelectric potential produced from the TENG can efficiently drive the transistors and logic devices without applying gate voltages. High performance tribotronic transistors are achieved with on/off ratio exceeding 106 and cutoff current below 1 pA μm^–1. Tunable electrical behaviors of the logic device are also realized, including tunable gains (improved to ≈13.8) and power consumptions (≈1 nW). This work offers an active, low‐power‐consuming, and universal approach to modulate semiconductor devices and logic circuits based on 2D materials with TENG, which can be used in microelectromechanical systems, human–machine interfacing, data processing and transmission.     

Ambipolar transistors based on azurin proteins

A new type of transistor is presented. It is realised by using a metalloprotein; namely, azurin. Thanks to their natural functional characteristics, which involve inter- and intramolecular electron transfer, metalloproteins are good candidates for biomolecular nanoelectronics. The implementation of a prototype of protein transistor operating in air and in the solid state based on self-organised films of azurins is reported. Experimental current-voltage characteristics are shown. The new device presents an ambipolar behaviour as the gate bias voltage is changed. Exploiting this peculiar characteristic, a fully integrated logic gate which can be a good starting point for a new class of nanoelectronics devices has been realised.     

Large area tunable arrays of graphene nanodots fabricated using diblock copolymer micelles

Nanostructured graphenes such as nanoribbons, nanomeshes, and nanodots have attracted a great deal of attention in relation to graphene-based semiconductor devices. The block copolymer micellar approach is a promising bottom-up technique for generating large area nanostructures of various materials without using sophisticated electron-beam lithography. Here we demonstrate the fabrication of an array of graphene nanodots with tunable size and inter-distance with the utilization of a monolayer of diblock copolymer micelles. Au nanoparticles were synthesized in the micellar cores and effectively worked as shielding nanostructures in generating graphene nanodots by oxygen plasma etching. We also controlled the radius and inter-distance of graphene nanodots simply through the molecular weight of the copolymers.     

A fully tunable single-walled carbon nanotube diode

We demonstrate a fully tunable diode structure utilizing a fully suspended single-walled carbon nanotube. The diode's turn-on voltage under forward bias can be continuously tuned up to 4.3 V by controlling gate voltages, which is ～6 times the nanotube band gap energy. Furthermore, the same device design can be configured into a backward diode by tuning the band-to-band tunneling current with gate voltages. A nanotube backward diode is demonstrated for the first time with nonlinearity exceeding the ideal diode. These results suggest that a tunable nanotube diode can be a unique building block for developing next generation programmable nanoelectronic logic and integrated circuits.     

Magnetization dynamics, throughput and energy dissipation in a universal multiferroic nanomagnetic logic gate with fan-in and fan-out

The switching dynamics of a multiferroic nanomagnetic NAND gate with fan-in/fan-out is simulated by solving the Landau-Lifshitz-Gilbert (LLG) equation while neglecting thermal fluctuation effects. The gate and logic wires are implemented with dipole-coupled two-phase (magnetostrictive/piezoelectric) multiferroic elements that are clocked with electrostatic potentials of ~50 mV applied to the piezoelectric layer generating 10.1 MPa stress in the magnetostrictive layers for switching. We show that a pipeline bit throughput rate of ~0.5 GHz is achievable with proper magnet layout and sinusoidal four-phase clocking. The gate operation is completed in 2 ns with a latency of 4 ns. The total (internal + external) energy dissipated for a single gate operation at this throughput rate is found to be only ~500 kT in the gate and ~1250 kT in the 12-magnet array comprising two input and two output wires for fan-in and fan-out. This makes it respectively three and five orders of magnitude more energy-efficient than complementary-metal-oxide-semiconductor-transistor (CMOS)-based and spin-transfer-torque-driven nanomagnet-based NAND gates. Finally, we show that the dissipation in the external clocking circuit can always be reduced asymptotically to zero using increasingly slow adiabatic clocking, such as by designing the RC time constant to be three orders of magnitude smaller than the clocking period. However, the internal dissipation in the device must remain and cannot be eliminated if we want to perform fault-tolerant classical computing.     

Liquid crystal holographic configurations for optically reconfigurable gate arrays

An optically reconfigurable gate array (ORGA) system, which consists of an ORGA very large scale integration (VLSI), an easily rewritable liquid crystal holographic memory recording four configuration contexts, and a laser array, is proposed. Circuits on a gate array of the ORGA-VLSI can be programmed rapidly by exploiting large parallel connections between a holographic memory and a gate array VLSI; that programming can be executed even as it is being programmed. Consequently, the gate array can be switched from a certain circuit to another circuit instantaneously. We present a demonstration of the ORGA system and experimental results.     

Hybrid Flexible Resistive Random Access Memory‐Gated Transistor for Novel Nonvolatile Data Storage

Here, a single‐device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three‐layered structure is fabricated by utilizing solution‐processed MoS₂ nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene‐based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well‐defined memory window. Compared to the reference flash memory device based on the MoS₂ floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM‐gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well‐defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high‐performance flexible electronics.     

Single-electron transistors based on gate-induced Si island for single-electron logic application

The island size dependence of the capacitance components of single-electron transistors (SETs) based on gate-induced Si islands was extracted from the electrical characteristics. In the fabricated SETs, the sidewall gate tunes the electrically induced tunnel junctions, and controls the phase of the Coulomb oscillation. The capacitance between the sidewall gate and the Si island extracted from the Coulomb oscillation phase shift of the SETs with sidewall depletion gates on a silicon-on-insulator nanowire was independent of the Si island size, which is consistent with the device structure. The Coulomb oscillation phase shift of the fabricated SETs has the potential for a complementary operation. As a possible application to single-electron logic, the complementary single-electron inverter and binary decision diagram operation on the basis of the Coulomb oscillation phase shift and the tunable tunnel junctions were demonstrated.     

Large array of sub-10-nm single-grain Au nanodots for use in nanotechnology

A uniform array of single-grain Au nanodots, as small as 5-8 nm, can be formed on silicon using e-beam lithography. The as-fabricated nanodots are amorphous, and thermal annealing converts them to pure Au single crystals covered with a thin SiO(2) layer. These findings are based on physical measurements, such as atomic force microscopy (AFM), atomic-resolution scanning transmission electron microscopy, and chemical techniques using energy dispersive X-ray spectroscopy. A self-assembled organic monolayer is grafted on the nanodots and characterized chemically with nanometric lateral resolution. The extended uniform array of nanodots is used as a new test-bed for molecular electronic devices.     

COSMOS-a novel MOS device paradigm

Downscaling alone is not sufficient to sustain the development of CMOS devices, and further paradigm shifts are necessary. In this paper, we argue such a shift is possible and show through technology computer-aided design simulations that a symmetrically operating CMOS device pair may be built under a single gate structure by a surprisingly simple choice of device layout and channel engineering parameters. As a result, we predict that another seemingly fundamental CMOS architectural requirement, the need to build two separate MOSFETs with individual gate stacks, may be eliminated. We call this new architecture a complementary orthogonal stacked MOS (COSMOS), which places the n and p MOSFETs perpendicular to one another under a single gate, integrating them vertically, as well as laterally. We demonstrate how the device may be built, operated, and optimized for symmetric operation, as well as verifying logic NOT operation via three-dimensional device simulations. The COSMOS architecture would not only mean significant savings in the active device area of a conventional digital CMOS layout, but also reductions in RC device parasitics associated with building and wiring two sets of devices for a single Boolean output function.     

High-speed Josephson integrated circuit technology

The author describes recent progress in high-speed integrated circuits using niobium junctions. He briefly describes the circuit fabrication process and then introduces the modified variable threshold logic (MVTL) gate family. The lowest experimentally obtained MVTL OR-gate delay was only 2.5 ps with a power consumption of 17 μW/gate. This gate family is used in various high-speed logic circuits, such as 8-bit shift registers, 16-bit ALUs (arithmetic logic units), and 4-bit microprocessors. The author confirmed the high-speed operation of less than 10 ps per gate on average for these circuits. A novel high-sensitivity magnetic sensor using a SQUID (superconducting quantum interference device) was also developed. It is called a single-chip SQUID magnetometer because the feedback circuit, which is operated at room temperature is a conventional SQUID system, has been integrated on the same chip as the SQUID sensor itself     

Growth of vertically aligned carbon nanofibers from nickel nanodot arrays produced from diblock copolymer thin film templates

Diblock copolymers of polystyrene and poly(methyl methacrylate) are utilized in a thin film to create a nanoscale template, which is used to deposit a nanoscale array of nickel nanodots. Systematic experiments show that this process must be optimized to successfully transfer the order of the diblock copolymer template to the resultant nickel nanodot array. It is found that the amount of nickel deposited dramatically impacts the fidelity of the final nanodot array, with a thickness ratio for copolymer:metal of 8:1 found to be optimal. The results also indicate that the method by which the surface is neutralized for the diblock domain alignment impacts the amount of nickel nanodots that remain on the surface after template removal. Finally, the nanoscale array of nickel nanodots is utilized to successfully grow vertically aligned carbon nanofibers from 18 nm and 40 nm diameter nickel dots.     

Concatenated All-optical Loop Mirror Switches

Abstract

Synthesis of a sharp switching characteristic is experimentally demonstrated by concatenation of nonlinear optical loop mirrors. A novel configuration has been used which results in three terminal operation of the device. This device can be used as a logic gate and for pulse shaping to produce square pulses.     

Crossed-film cryotron switching speed

To date there have been no direct measurements of the switching speed of an individual crossed-film cryotron (CFC) due to the extremely low gate resistance of the device in its normal state. A method which is, in principle, similar to conventional sampling techniques is used to determine the CFC switching speed with a 2-ns time resolution and a gate resistance sensitivity of 0.1 μΩ. CFC switching speeds are determined as a function of control current overdrive and gate current. In this way, the gain-bandwidth limitations of the device are experimentally determined. These data can be used to determine the optimum speeds of CFC logic circuits.