一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对p MOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于p MOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是p MOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对pMOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于pMOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是pMOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

Bias temperature instability in hydrogenated thin-film transistors

The bias temperature instability is studied in hydrogenated n- and p-channel thin-film MOS transistors (TFT's) fabricated using a low-temperature process compatible with active matrix liquid crystal display application. We observe significant threshold voltage and subthreshold slope degradation under both positive and negative bias stress. The degradation increases with increased hydrogen incorporation and is temperature and electric field activated. The experimental results are explained based on trap creation model which depends on the hydrogen content of the device     

Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation

The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.      

Reliability of MOSFETs as affected by the interface traptransformation process

An investigation of the long-term time-dependent degradation of the subthreshold characteristics in n-channel and p-channel MOSFETs resulting from Fowler-Nordheim electron injection is discussed. Immediately after the hot-electron injection, degradation in both n- and p-channel transistors due to the hot-electron-induced interface traps is observed. When measured after the hot-electron injection was terminated, however, the subthreshold slope in n-channel transistors exhibits a gradual recovery toward its preinjection level, while that in p-channel transistors continues to degrade with time. This phenomenon can be explained by the interface trap transformation process, which is characterized by a gradual reduction of the hot-electron-induced interface traps above midgap and a gradual increase of the interface traps below midgap     

Consistent model for the hot-carrier degradation in n-channel andp-channel MOSFETs

A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. For n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection (V_g≈V_t) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps. The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model     

Bias temperature reliability of p-channel high-voltage devices

Important shifts in the threshold voltage of high voltage p-channel DMOS transistors have been observed. These shifts are strongly dependent on the stress conditions.An empirical degradation model is derived from measurement data. For a given allowed shift in threshold voltage, this model can determine the safe operating area of the device.The shift in threshold voltage in the p-channel DMOS transistors is explained by excitation and trapping of holes at the oxide-silicon interface at the drain side.     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

A general gate-current p-MOS lifetime prediction method applicableto different channel structures

A recently developed surface-channel p-MOS lifetime prediction technique based on injection gate charge is extended to buried-channel devices. It is shown that a more general form of the equation governing the degradation accurately describes the degradation behavior of both surface-channel and buried-channel transistors, indicating that the method has general applicability for p-channel transistors     

Mechanism of device degradation in n- and p-channel polysiliconTFTs by electrical stressing

The effects of electrical stress on hydrogenated n- and p-channel polysilicon thin-film transistors are discussed. The on-state caused the most significant degradation, whereas off-state and accumulation conditions resulted in negligible degradation. The on-state stress degraded the threshold voltage, trap state density, and subthreshold sharpness of both n- and p-channel devices toward perhydrogenated values, and the rates of degradation increased with stressing biases. The field-effect mobility and leakage current, however, were not degraded by stressing. The mechanism of device degradation may be attributed to the metastable creation of midgap states within the polysilicon channel, as opposed to gate dielectric charge trapping or interface state generation     

A Reliability Model for Low-Temperature Polycrystalline Silicon Thin-Film Transistors

We proposed here a reliability model that successfully introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.      

Analysis of the charge pumping technique and its application forthe evaluation of MOSFET degradation

It is shown that the charge pumping technique is able not only to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (e.g., irradiation, hot-carrier, Fowler-Nordheim stress), but also in several cases to evaluate and to quantify the degradation. It is further shown that the technique can be applied to separate the presence of fixed oxide changes due to charge trapping and the generation of interface traps. It can be used to analyze degradations that occur uniformly over the transistor channel, as well as strongly localized transistor degradations (e.g., for the case of hot-carrier degradations). All possible cases of uniform and nonuniform degradations, for p-channel as well as for n-channel transistors, are described, and for most of them experimental examples are given     

MOS Integrated Circuit Reliability

This paper presents information on the reliability of MOS integrated circuits based on p-channel enhancement-mode transistors, and describes their failure modes and mechanisms. The principal failure mechanisms were ion migration at the surface and oxide shorting. The results of experimental studies of the effects of variations in construction, processing, and levels of stress are presented, and are compared with other available information on MOS integrated circuit reliability. The failure rate for commercially available complex MOS arrays is on the order of 0.001 to 0.01 per 1000 h of operating life at 125°C for arrays containing approximately 600 p-channel transistors. This corresponds to a failure rate on the order of 5 × 10?6 to 5 × 10?5 per equivalent gate per 1000 h. The effects of device complexity, operating temperature, and other factors are discussed. A reliability prediction equation for MOS integrated circuits is derived from available information. An overall activation energy for functional failure mechanisms of approximately 5 kcal/mole (?0.2 eV/molecule) is considered applicable to typical MOS integrated circuits. Thus, the failure rate of MOS devices operated at 50°C ambient temperature can be predicted to be on the order of 10?6 to 10?5 per equivalent gate per 1000 h.     

Dynamic NBTI characteristics of PMOSFETs with PE-SiN capping

Negative-bias-temperature instability (NBTI) characteristics of strained p-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) under dynamic and AC stressing were investigated in this work. The compressive strain in the channel was deliberately induced by a plasma-enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) capping layer in this study. It was found that the capping would degrade the NBTI characteristics, although the degradation is relieved when the stress frequency increases. The aggravated NBTI behaviors are ascribed to the higher amount of hydrogen incorporation during SiN deposition.     

Role of nitridation/reoxidation of NH3-nitrided gatedielectrics on the hot-carrier resistance of CMOS transistors

The effect of nitriding and reoxidizing conditions are examined on the hot-carrier (HC) properties of p-channel and n-channel transistors with reoxidized nitrided oxide gate dielectrics. Nitrogen was introduced into the gate dielectric by performing cyclical nitridation and reoxidation steps (one cycle versus four cycles of nit./reox.), keeping the same overall oxidation and nitridation times constant, It was found that there were considerable differences in hot-carrier hardness, of up to three orders of magnitude for p-channel transistors, but much less for n-channel devices. Nitrogen-content variations (a factor of 2) for these very similar conditions explain the n-channel hot-carrier results. In the case of the p-MOS transistors, it is suggested that changes in hydrogen concentration might be responsible for the hot-carrier behavior     

An accurate CAD model for the ambipolar a-Si: H TFT

The ambipolar output drain current versus drain voltage characteristics of hydrogenated amorphous silicon thin-film transistors are modeled by a method intended for use in computer-aided design programs. An accurate model has been developed that uses a modified experimental sheet conductivity curve to predict the output drain characteristics over many orders of magnitude of the drain current in both the n-channel and p-channel modes of operation. Analytical expressions for the drain current are developed.     

Short-channel pMOSTs in a high-resistivity silicon substrate. II.Noise performance

For pt.I, see ibid., vol.39, no.10, p.2268-77 (1992). The noise performance, important for the use of p-channel transistors on high-resistivity silicon in analog applications, is investigated. This is done for the two operation modes: bulk (|V_gs|<|V_T|) and surface (| V_gs|>|V_T|). For the studied transistors, both modes are characterized by a 1/f noise spectrum extending to frequencies of up to ≈100 Hz, and followed by a white-noise spectrum, determined by the substrate resistance     

Modeling and characterization of CMOS-compatible high-voltage device structures

The design, implementation, and modeling of high-voltage MOS transistors in a Standard CMOS technology is described. High voltage n- and p-channel transistors, with breakdown voltages of 50 and 180 V, respectively, have been fabricated. A SPICE-compatible model for these transistors is described, and its accuracy verified by comparison with experimental results.     

Parasitic transistor effects in CMOS VLSI

Parasitic field-effect transistor (FETs) and bipolar junction transistors (BJTs) in a CMOS circuit are described, along with their interactions with each other and their effect on circuit performance. The results are considered to be useful for setting up design rules between n-channel and p-channel active transistors in CMOS IC layout. Novel parasitic transistors associated with next-generation VLSI technologies, such as trench isolation and silicon-on-insulator, are discussed briefly     

An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I²L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (leq 2 microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n⁺buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.