Effect of dislocations on performance of LWIR HgCdTe photodiodes

The epitaxial growth of HgCdTe on alternative substrates has emerged as an enabling technology for the fabrication of large-area infrared (IR) focal plane arrays (FPAs). One key technical issue is high dislocation densities in HgCdTe epilayers grown on alternative substrates. This is particularly important with regards to the growth of HgCdTe on heteroepitaxial Si-based substrates, which have a higher dislocation density than the bulk CdZnTe substrates typically used for epitaxial HgCdTe material growth. In the paper a simple model of dislocations as cylindrical regions confined by surfaces with definite surface recombination is proposed. Both radius of dislocations and its surface recombination velocity are determined by comparison of theoretical predictions with carrier lifetime experimental data described by other authors. It is observed that the carrier lifetime depends strongly on recombination velocity; whereas the dependence of the carrier lifetime on dislocation core radius is weaker. The minority carrier lifetime is approximately inversely proportional to the dislocation density for densities higher than 10⁵ cm⁻². Below this value, the minority carrier lifetime does not change with dislocation density. The influence of dislocation density on the R₀A product of long wavelength infrared (LWIR) HgCdTe photodiodes is also discussed. It is also shown that parameters of dislocations have a strong effect on the R₀A product at temperature around 77 K in the range of dislocation density above 10⁶ cm⁻². The quantum efficiency is not a strong function of dislocation density.     

Key performance-limiting defects in P-on-N HgCdTe LPE heterojunction infrared photodiodes

The operability of long-wavelength p-on-n double layer heterojunction arrays for 40K low-background applications has long been limited by the wide variation in pixel-to-pixel zero bias resistance (R_o) values. Diodes on test structures showing lower performance, with R_o values below 7 × 10⁶ ohm at 40K, usually contained gross metallurgical defects such as dislocation clusters and loops, pin holes, striations, Te inclusions, and heavy terracing. However, diodes with R_o values between 7 × 10⁶ and 1× 10⁹ ohm at 40K contained no visible defects. To study the “invisible” performance-limiting defects (i.e. defects that cannot be revealed by etching), a good correlation between the dynamic resistance at 50 mV reverse bias (R50) value at 77K and the R_o value at 40K was first established, and then used as a tool. The correlation allowed measurements of a large number of devices at 77K, rather than relying exclusively on time-consuming measurements at 40K. Interesting results regarding R_o values at 40K, such as insensitivity to low-density dislocations, mild degradation from Hg vacancies, severe degradation from Hg interstitials, and correlation with junction positioning, were obtained from specially designed experiments.     

Modeling of the zero-bias resistance-area product of long wavelength infrared HgCdTe-on-Si diodes fabricated from molecular beam epitaxy-grown epitaxial layers

The electrical effects of dislocations has been studied by modeling zero-bias resistance-area product (R₀A) of long wavelength infrared diodes fabricated in molecular beam epitaxy (MBE)-grown HgCdTe-Si epitaxial films. Results show that dislocations influence both 40 K and 78 K R₀A products in high dislocation density (HgCdTe/Si) material. In low dislocation density samples (HgCdTe/CdZnTe), the variations in 78 K R₀A are limited by the composition (x) variations in Hg_1-xCd_xTe material, whereas dislocation contribution dominates the variations at 40 K. The origin of relatively large spread in 40 K R₀A in both types of samples is traced to the statistical variations in the core charges of dislocations. It is concluded that additional alternatives besides the reduction of dislocation density (such as control of core charges), may also need attention in order to make Si a viable substrate material for the growth of HgCdTe epitaxial layers suitable for devices operating at 40 K.     

Effect of crystallographic defects on the reverse performance of 4H-SiC JBS diodes

A quantitative analysis of the effect of crystallographic defects on the performance of 4H-SiC junction barrier Schottky (JBS) diodes was performed. It has been shown that higher leakage current in diodes is associated with a greater number of elementary screw dislocations. Further, threading dislocation pair arrays were observed in some of the fabricated devices and, for the first time, the role of such defects on JBS reverse leakage currents is investigated.     

Long wavelength infrared, molecular beam epitaxy, HgCdTe-on-Si diode performance

In the past several years, we have made significant progress in the growth of CdTe buffer layers on Si wafers using molecular beam epitaxy (MBE) as well as the growth of HgCdTe onto this substrate as an alternative to the growth of HgCdTe on bulk CdZnTe wafers. These developments have focused primarily on mid-wavelength infrared (MWIR) HgCdTe and have led to successful demonstrations of high-performance 1024×1024 focal plane arrays (FPAs) using Rockwell Scientific’s double-layer planar heterostructure (DLPH) architecture. We are currently attempting to extend the HgCdTe-on-Si technology to the long wavelength infrared (LWIR) and very long wavelength infrared (VLWIR) regimes. This is made difficult because the large lattice-parameter mismatch between Si and CdTe/HgCdTe results in a high density of threading dislocations (typically, >5E6 cm⁻²), and these dislocations act as conductive pathways for tunneling currents that reduce the R_oA and increase the dark current of the diodes. To assess the current state of the LWIR art, we fabricated a set of test diodes from LWIR HgCdTe grown on Si. Silicon wafers with either CdTe or CdSeTe buffer layers were used. Test results at both 78 K and 40 K are presented and discussed in terms of threading dislocation density. Diode characteristics are compared with LWIR HgCdTe grown on bulk CdZnTe.     

Material properties of Pb1-xSnxSe epilayers on Si and their correlation with the performance of infrared photodiodes

Hall mobilities and resistance area products R_oA of infrared diodes in epitaxial Pb_1-xSn_xSe layers on CaF₂ covered Si(111) substrates were correlated with threading dislocation densities p. The low temperature saturation Hall mobilities were entirely determined by p and proportional to their mean spacing 1/ √ρ. For the photodiodes, the R₀A values at low temperatures were inversely propor-tional to ρ. A model where each dislocation in the active area of the diodes causes a shunt resistance correctly describes the results, the value of this resistance for a single dislocation is 1.2 GΩ for PbSe at 85K. The dislocation densities were in the 2 × 10⁷ to 5 × 10⁸cm^-2 range for the 3-4 μm thick as-grown layers. Higher R₀A values are obtainable by lowering these densities by thermal annealing, which sweeps the threading ends of the misfit dislocations to the edges of the sample.     

Realization of very long wavelength infrared photovoltaic detector arrays on mercury cadmium telluride epitaxial layers grown on Si substrates

This paper proposes a development of n-on-p structures for realizing very long wavelength infrared (VLWIR) detector arrays on mercury cadmium telluride (HgCdTe) epitaxial layers grown on Si substrates. It is shown from a comparative study of zero-bias resistance-area product (R₀A) of diodes in n-on-p and p-on-n configurations that the n-on-p structure has promising potential to control contribution of dislocations, without actually reducing dislocation density below the current level (mid-10⁶ cm⁻²) of HgCdTe/Si material technology. The resulting gain will be in terms of both higher numerical magnitudes of R₀A and its reduced scatter.     

Electron and hole traps in GaN p-i-n photodetectors grown by reactive molecular beam epitaxy

GaN p-i-n photodetectors grown on sapphire by reactive molecular beam epitaxy have been characterized by measurements of room-temperature current-voltage (I-V), temperature-dependent capacitance (C-V-T), and deep level transient spectroscopy (DLTS) under both majority and minority carrier injection. Due to what we believe to be threading dislocations, the reverse I-V curves of p-i-n photodetectors show typical electric-field enhanced soft breakdown characteristics. A carrier freeze-out due to the de-ionization of Mg-related deep acceptors has been found by C-V-T measurements. Three electron traps, B (0.61 eV), D (0.23 eV), and E₁ (0.25 eV) and one hole trap, H₃ (0.79 eV) have been revealed by DLTS measurements. The photodetectors with lower leakage currents usually show higher responsivity and lower trap densities of D and E₁.     

The movement of surface dislocation loops in GaAs by the application of an electric field

Results which show that surface dislocation loops in GaAs may be moved by the application of high electric fields are presented. These results show the feasability of a degradation mechanism for high-field GaAs devices based on the multiplication of dislocations by the piezoelectric stresses produced in the material.     

Low threading dislocation density GaAs on Si(100) with InGaAs/GaAs strained-layer superlattice grown by migration-enhanced epitaxy

This paper reports a promising approach for reducing the density of threading dislocations in GaAs on Si. In _x Ga_1-x As/GaAs strained-layer superlattices (SLSs) grown by migration-enhanced epitaxy at 300° C on GaAs/Si acted as barriers to threading dislocations. Unlike conventional high-temperature-grown SLSs, the low-temperature-grown SLSs were hardly relaxed by the formation of misfit dislocations at GaAs/SLS interfaces, and this allowed them to accumulate considerable strain. New threading dislocation generation due to the misfit dislocation was also suppressed. These factors caused effective bending of threading dislocations and significantly reduced the dislocation density. For the samples that had an SLS withx = 0.3, the average etch-pit density was 7 × 10⁴ cm^-2, which is comparable to that of GaAs substrates.     

Threading and misfit-dislocation motion in molecular-beam epitaxy-grown HgCdTe epilayers

Lattice mismatch between the substrate and the absorber layer in single-color HgCdTe infrared (IR) detectors and between band 1 and band 2 in two-color detectors results in the formation of crosshatch lines on the surface and an array of misfit dislocations at the epi-interfaces. Threading dislocations originating in the substrate can also bend into the interface plane and result in misfit dislocations because of the lattice mismatch. The existence of dislocations threading through the junction region of HgCdTe IR-photovoltaic detectors can greatly affect device performance. High-quality CdZnTe substrates and controlled molecular-beam epitaxy (MBE) growth of HgCdTe can result in very low threading-dislocation densities as measured by the etch-pit density (EPD ∼ 10⁴cm⁻²). However, dislocation gettering to regions of high stress (such as etched holes, voids, and implanted-junction regions) at elevated-processing temperatures can result in a high density of dislocations in the junction region that can greatly reduce detector performance. We have performed experiments to determine if the dislocations that getter to these regions of high stress are misfit dislocations at the substrate/absorber interface that have a threading component extending to the upper surface of the epilayer, or if the dislocations originate at the cap/absorber interface as misfit dislocations. The preceding mechanisms for dislocation motion are discussed in detail, and the possible diode-performance consequences are explored.     

Defects and defect reduction processing in semiconductor heterostructures

Defects such as dislocations and interfaces play a crucial role in the performance of heterostructure devices. The full potential of GaAs on Si heterostructures can only be realized by controlling the defect density. The nature of misfit dislocations at the heterointerface has been studied and a mechanism for the formation of 60° and 90° misfit dislocations has been proposed. Threading dislocations in the epilayer are the most prominent defects and their density has to be controlled to fully utilize the properties of semiconductor heterostructures. Various processes to reduce defect densities in the epilayers have been discussed and in particular, the use of strained layer superlattices to reduce the threading dislocation density has been presented in this paper. Several superlattice structures have been used to reduce the density of threading dislocations in the GaAs epilayer. In this study, we have optimized the use of strained layer superlattices with respect to the position, period and number to reduce and control the dislocation density. The use of strained layer superlattices in conjunction with rapid thermal annealing was found to be the most effective method in reducing threading dislocation density. Transmission electron microscopy has been used to study the dislocation density reduction and the interaction of threading dislocations with the strained layers.     

Metallurgical amd electroluminescence characteristics of vapor-phase and liquid-phase epitaxial junction structures of InxGa1−xAs

In_xGa_1−xAs (x = 0.05 to 0.32) p-n junction structures have been grown on GaAs substrates by vapor-phase epitaxy (VPE) and liquid-phase epitaxy (LPE). It is shown that by step-grading the VPE material, lattice-mismatch strain can be absorbed by dislocations at the grading interfaces, leaving the final constant-composition device layers relatively dislocation free. In contrast, the dislocation density for LPE In_xGa_1−xAs increases with increasing InAs concentration. For both materials, diffusion lengths, electroluminescence efficiencies, and 77°K laser-diode parameters (threshold and efficiency) can be correlated with their dislocation densities. The VPE materials have electrical and luminescence properties that are independent of InAs concentration, and match those of their GaAs counterparts. The LPE materials exhibit properties that degrade with increasing InAs concentration. This research was supported in part by the Air Force Avionics Laboratory, WPAFB, Ohio, under Contract No. F33615-73-C-1177     

Dynamical X-ray Diffraction from ZnS y Se1?y /GaAs (001) Multilayers and Superlattices with Dislocations

High-resolution x-ray diffraction is a valuable nondestructive tool for structural characterization of semiconductor heterostructures, and the diffraction profiles contain information on the depth profiles of strain, composition, and defect densities in device structures. Much of this information goes untapped because the lack of phase information prevents direct inversion of the diffraction profile. The current practice is to use dynamical simulations in conjunction with a curve-fitting procedure to indirectly extract the profiles of strain and composition. These dynamical simulations have been based on perfect, dislocation-free laminar crystals, rendering the analysis inapplicable to structures having dislocation densities greater than about 10⁶?cm^?2. In this work we present a dynamical model for Bragg x-ray diffraction in semiconductor device structures with nonuniform composition, strain, and dislocation density, which is based on the Takagi–Taupin equation for distorted crystals and accounts for the angular and strain broadening of dislocations. We show that the x-ray diffraction profiles from ZnS _y Se_1?y multilayers and superlattices are strongly affected by the depth distribution of the dislocation density as well as the composition, suggesting that it should be possible to extract the profiles of composition, strain, and dislocation density by the analysis of measured diffraction profiles.     

HgCdTe mid-wavelength IR photovoltaic detectors fabricated using plasma induced junction technology

Preliminary characterization results are presented for mid-wave infrared (MWIR) mercury cadmium telluride n-on-p photodiodes fabricated using a plasma induced type conversion junction formation technology. The diodes have been fabricated on three different vacancy doped p-type epitaxial starting materials, grown by liquid phase epitaxy (LPE) on CdZnTe, LPE on sapphire, and P/p isotype heterojunction material grown by molecular beam epitaxy (MBE) on CdZnTe. All materials had CdTe mole fraction in the active region of the device of ∼0.3. The process uses a H₂/CH₄ plasma generated in a parallel plate reactive ion etching (RIE) system to type convert the p-type material to n-type. The process is different from previously reported type conversion techniques in that it does not require a high temperature anneal, does not expose the junction at the surface to atmosphere after formation, and requires significantly fewer process steps than other planar processes. Homojunction devices fabricated using this process exhibit R₀A values >10⁷ Ω·cm² at 80 K. The R₀A is diffusion limited for temperatures >∼135 K. Results for responsivity, bias dependence of dynamic resistance — junction area product and 1/f noise show that the resulting diodes are comparable to the best planar diodes reported in the literature.     

VLWIR HgCdTe detector current-voltage analysis

This article details current-voltage characteristics for a very long wavelength infrared (VLWIR) Hg_1−x Cd_xTe detector from Raytheon Vision Systems with a cutoff wavelength of 20.0 μm at 28 K. In this article, the VLWIR detector diode currents are modeled as a function of bias and temperature. This in-depth current model includes diffusion, band-to-band tunneling, trap-assisted tunneling (TAT), and shunt currents. The trap density has been extracted from the modeled TAT component of the current and was revealed to be relatively temperature-independent. An attempted incorporation of VLWIR detector susceptibility to stress has also been included through variation of the model parameter associated with the p-n junction electric field strength. This field variation accounts for stress induced piezoelectric fields. The current in this VLWIR detector was found to be diffusion-limited under much of the temperature and bias ranges analyzed. This modeling allows the scrutiny of both the dominant current-limiting mechanism and the magnitudes of the various current components as a function of both bias and temperature, allowing the straightforward determination of the ideal operating conditions for a given detector.     

The thermal stability of lattice mismatched InGaAs grown on patterned GaAs

Patterning and etching substrates into mesas separated by trenches before the growth of mismatched (by about 1% or less) epitaxial layers considerably reduces the interface misfit dislocation density when the layer thickness exceeds the critical thickness. Such films are in a metastable state, since misfit dislocations allow the epitaxial layers to relax to an in-plane lattice parameter closer to its strain-free value. Thermal annealing (from 600 to 850° C) has been used to study the stability of these structures to explore the properties of the misfit dislocations and their formation. The misfit dislocation density was determined by counting the dark line defects at the InGaAs/GaAs interface, imaged by scanning cathodoluminescence. InGaAs epitaxial layers grown on patterned GaAs substrates by organometallic chemical vapor deposition possess a very small as-grown misfit dislocation density, and even after severe annealing for up to 300 sec at 800° C the defect density is less than 1500 cm⁻¹ for a In_0.04Ga_0.96As, 300 nm thick layer (about 25% of the dislocation density found in unpatterned material that has not been annealed). The misfit dislocation nucleation properties of the material are found to depend on the trench depth; samples made with deeper (greater than 0.5 μm) trenches are more stable. Molecular beam epitaxially grown layers are much less stable than the above material; misfit dislocations nucleate in much greater numbers than in comparable organo-metallic chemical vapor deposited material at all of the temperatures studied.     

Design of Dislocation-Compensated ZnS y Se1−y /GaAs (001) Heterostructures

The understanding of lattice relaxation and dislocation dynamics in lattice-mismatched semiconductors makes it possible to design metamorphic device structures utilizing the dislocation compensation mechanism for reduced defects, improved performance, and enhanced reliability. We have developed a dislocation dynamics model accounting for misfit–threading interactions and have applied it to ZnS _y Se_1?y /GaAs (001) heterostructures.1 Dislocation compensation involves the removal of threading dislocations associated with one sense of misfit dislocations by bending them over to create misfit dislocations of the opposite sense at an intentionally mismatched interface. Here we investigated the design of dislocation-compensated ZnS _y Se_1?y /GaAs (001) heterostructures and considered the sulfur mole fraction tolerances applicable to such structures. We considered two types of structures: type A involved a uniform-composition (ungraded) layer on top of a uniform-composition buffer, while type B involved a uniform-composition layer on a linearly graded buffer. For each structure type we studied the requirements on the thickness and compositional profile of the buffer layer to optimize the removal of mobile threading dislocations from the top uniform (device) layer as well as the allowed tolerance in compositional overshoot to achieve structures with low threading dislocation density. We show for both types of structure that (i) for given compositional overshoot at the buffer–device layer interface, there is an optimum buffer thickness which minimizes the dislocation density; and (ii) for given buffer thickness there is an optimum overshoot which minimizes the dislocation density.     

Electrical and material quality ofSi1-xGex/Si p-N heterojunctions produced bylimited reaction processing

Si_1-xGe_x/Si p-N heterojunctions prepared by a chemical vapor deposition technique, limited reaction processing (LRP) were characterized using DC electrical measurements, transmission electron microscopy (TEM), and X-ray topography. Heterojunctions with Si _1-xGe_x layer thickness ranging from 52 to 295 nm and a constant Ge fraction of 23% were fabricated to study the effect of increasing the number of misfit dislocations on the device characteristics. Devices with the thinnest layers (⩽120 nm) display forward characteristics with ideality factors of 1.01 and reverse leakage current densities of less than 4 nA/cm for a 5-V reverse bias. These thin-layer devices have dislocation spacings greater than 10 μm. Devices utilizing Si_1-xGe_x layers thicker than 200 nm have forward characteristics which clearly display the presence of recombination currents, and reverse leakage current densities greater than 290 nA/cm² at -5 V. The dislocation spacing in these devices is less than 1 μm. Ideal characteristics were found at room temperature in devices known to contain dislocations     

Anomalous junction leakage current induced by STI dislocations andits impact on dynamic random access memory devices

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction