基于SIMD部件的四倍精度浮点乘加器设计

如何减少四倍精度浮点运算的硬件开销和延迟是需要解决的重要问题。为减少四倍精度乘加器的硬件开销,基于支持64位×4的双精度浮点SIMD FMA部件,设计并实现了一种新的四倍精度浮点乘加器(QPFMA),来支持4种浮点乘加运算和乘法、加减法、比较运算,运算延迟为7拍。通过将四倍精度113位×113位尾数乘法器分解为4个57位×57位乘法器来共享双精度浮点SIMD FMA部件的53位×53位乘法器,显著减少了实现QPFMA的硬件开销。基于65nm工艺的逻辑综合结果表明,该QPFMA频率可达1.1GHz,面积是常规QPFMA设计的42.71％,仅与一个双精度浮点乘加器相当。与现有的QPFMA设计相比,相当工艺和频率下,其运算延迟减少了3拍,门数减少了65.96％。     

M-DSP中高性能浮点乘加器的设计与实现

针对高性能M型数字信号处理器（M-DSP）对浮点运算的性能、面积和功耗要求,研究分析了M-DSP总体结构和浮点运算的指令特点,设计和实现了一种高性能低功耗的浮点乘累加器（FMAC）。该乘加器采用单、双精度通路分离的主体结构,分为六级流水站执行,对乘法器、对阶移位等关键模块进行了复用设计,支持双精度和单精度浮点乘法、乘累加、乘累减、单精度点积和复数运算。对所设计的乘加器进行了全面的验证,基于45nm工艺采用Synopsys公司的Design Compiler工具综合所设计的代码,综合结果表明运行频率可达1GHz,单元面积36856μm²;与FT-XDSP中的乘加器相比,面积节省了12.95%,关键路径长度减少了2.17%。     

分离通路浮点乘加器设计与实现

针对传统浮点融合乘加器会增加独立浮点加减法、乘法等运算延迟的缺点,首先设计并实现了一种分离通路浮点乘加器SPFMA,通过分离乘法和加法通路,在保持融合乘加运算延迟6拍延迟不变的情况下,将独立乘法和加法等运算延迟由6拍减为4拍,克服了传统融合乘加器的缺点。然后经专用工艺单元库逻辑综合评估,SPFMA可工作在1.2GHz以上,面积60779.44um²。最后在硬件仿真加速器平台上运行SPEC CPU2000浮点测试课题对其进行性能评估,结果表明所有浮点课题性能均有所提高,最大提高5.25％,平均提高1.61％,证明SPFMA可进一步提高浮点性能。     

可重构浮点混合/连续乘-加器的设计与实现

浮点连续乘-加、混合乘-加和三操作数加等浮点算术运算在科学计算领域中应用越来越频繁,为设计一款支持浮点连续乘-加、混合乘-加和三操作数加的多功能浮点运算单元,提出一种可重构浮点混合/连续乘-加器,通过对控制位的配置可以实现多种浮点数据操作。该乘-加器采用8级流水线,可以实现单周期的浮点乘累加,大幅提高数据处理吞吐量,同时支持三操作数加和两操作数和的累加。在Modelsim SE6.6f中对该设计进行仿真验证,结果表明其能够在Xilinx Virtex-6 FPGA上实现,资源消耗2 631个LUT,频率可达250 MHz,结果证明该浮点混合/连续乘-加器具有较大的使用价值。     

基于VHDL的浮点算法研究

浮点运算是数字信号处理中最基本的运算,但因为现行EDA软件没有提供浮点运算功能,使其在FPGA中的实现却是个棘手问题.文中提出了一种基于VHDL的高精度浮点算法,并以9位实序列为例,通过浮点数表示、对阶操作、尾数运算以及规格化处理等步骤高效并准确地实现浮点加/减法、乘法、除法以及平方根等运算,最后在FPGA中下载并实现了上述浮点运算,并给出测试结果.测试数据表明:所设计的浮点算法在其浮点数位宽所对应的精度范围内,可以在FPGA上成功地实现包含加、减、乘、除及求平方根等各种浮点运算.     

浮点乘加部件延迟对浮点性能影响的研究

浮点融合乘加部件会增加独立浮点加减法、乘法等运算延迟.为克服该缺陷,研究将乘加部件独立乘法、加减法等运算延迟由6拍减为4拍时对浮点性能的影响.以某支持乘加运算的国产处理器为基础,修改相关的RTL级设计代码,利用硬件仿真加速器平台,对SPEC CPU2000浮点测试课题进行评估.实验结果表明,该延迟优化有利于提高浮点性能,最大提高5.25％,平均提高1.61％.     

一种低延迟高吞吐率的浮点整型乘累加单元

针对目前浮点运算单元在处理向量点乘运算时存在数据相关性的问题,提出一种低延迟单周期的累加单元结构.该结构用于7级流水的可配置乘累加单元,可兼容双精度浮点、双单精度浮点以及32位有符号数,且能对后置模块进行操作数隔离与门控时钟的低功耗处理.在Viterx-4平台上实验结果表明,该结构具有高性能、低延迟、单周期完成数据吞吐等特点,与使用Xilinx浮点IP的设计面积相比,时间积减少30％以上.     

支持超越函数的浮点运算单元的设计与实现

介绍自主设计的龙腾C2微处理器中浮点运算单元的设计与实现。该处理器与Intel80486DX4指令系统兼容,支持IEEE754标准扩展精度的浮点基本函数和超越函数运算。介绍了浮点运算单元的结构,分析了实现超越函数的高精度CORDIC算法的流程,讨论了实现浮点超越函数运算的数据通路和控制通路结构,并给出了仿真结果和精度评估结果。仿真和分析的结果表明,浮点运算单元的设计满足龙腾C2微处理器的设计要求。     

支持超越函数的浮点运算单元的设计与实现

介绍自主设计的龙腾C2微处理器中浮点运算单元的设计与实现.该处理器与Intel 80486DX4指令系统兼容,支持IEEE 754标准扩展精度的浮点基本函数和超越函数运算.介绍了浮点运算单元的结构,分析了实现超越函数的高精度CORDIC算法的流程,讨论了实现浮点超越函数运算的数据通路和控制通路结构,并给出了仿真结果和精度评估结果.仿真和分析的结果表明,浮点运算单元的设计满足龙腾C2微处理器的设计要求.     

一种快速SIMD浮点乘加器的设计与实现

本文设计和实现了5级全流水SIMD浮点乘加器,支持双精度和双单精度浮点乘法、乘累加(减)操作,用Modelsim和NC Verilog测试和验证了RTL代码实现,基于65nm工艺采用Synopsys公司的Design Complier工具综合硬件实现,运行频率可达714.286MHz。结果表明,相比文献[3]中经典的低延迟乘加结构,在相同综合条件下性能提升了17.89%,面积增加了6.61%,功耗降低了25.08%。     

基于FPGA的高精度科学计算加速器研究

探索了 FPGA平台加速高精度科学计算应用的能力和灵活性.首先,研究科学计算中最常用的操作——向量内积,提出基于定点操作的精确向量内积算法.以IEEE 754-2008标准的四精度(Quadruple Precision)浮点算术为例,在FPGA平台上设计了一个基于全展开方法的全流水四精度浮点乘累加单元(QPMAC):提出两级存储策略精确存储乘累加和;采用保留进位累加策略减少定点加法器位宽、简化进位处理、优化关键路径;引入累加和划分策略,实现流水吞吐率.最后,在XC5VLX330 FPGA芯片上设计一个LU分解和MGS-QR分解加速器原型来验证QPMAC的性能.实验结果表明,与运行在Intel四核处理器上的基于OpenMP的并行算法相比,集成4个QP-MAC单元的加速器能获得42倍到97倍的性能提升,并且能获得更高结果精度和更低能量消耗.     

高吞吐率浮点FFT处理器的FPGA实现研究

受浮点操作的长流水线延迟及FPGA片上RAM端口数目的限制,传统H可处理器的吞吐率通常只能达到每周期输出一个复数结果。本文用FPGA设计并实现了一种高吞吐率的IEEE754标准单精度浮点FFT处理器,通过改进蝶形计算单元的结构并重新组织FPGA片上RAM的访问,该处理器每周期平均可输出约两个复数计算结果,吞吐率约为传统FFT处理器吞吐率的两倍。对于1024点FFT变换,可在（512＋10）＊10=5220周期内完成。     

高效结构的多输入浮点乘法器在FPGA上的实现

传统的多输入浮点乘法运算是通过级联二输入浮点乘法器来实现的,这种结构不可避免地使运算时延和所需逻辑资源成倍增加,从而难以满足高速数字信号处理的需求。本文提出了一种适合于在FPGA上实现的浮点数据格式和可以在三级流水线内完成的一种高效的多输入浮点乘法器结构,并给出了在Xilinx公司Virtex系列芯片上的测试数据。     

Program-based dynamic precision selection framework with a dual-mode unified shader for mobile GPUs

To extend the life of battery-driven mobile devices while maintaining image quality, this work proposes a Program-based Dynamic Precision Selection (PDPS) framework with a dual-mode unified shader. Since fixed-point arithmetic can be performed faster and more energy-efficiently than floating-point arithmetic on power-limited devices, the use of fixed-point rather than floating-point rendering is a critical concern. The proposed PDPS framework is composed of a runtime profile-based mechanism for automatically determining the precision of each shading program in fixed-point arithmetic. Additionally, a scene change detection mechanism is developed to recalculate the rendering precision whenever a 3D scene changes. The results reveal an average 18% reduction in energy and 35% faster performance under fixed-point rendering. The degradation in rendered image quality under the proposed PDPS cannot be detected by the naked eye, and the PSNR is an average of 15% better than that achieved using related approach.     

Dual-mode floating-point adder architectures

Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower precision additions. A double precision floating-point adder implemented with the improved single-path algorithm is modified to design a dual-mode double precision floating-point adder that supports both one double precision addition and two parallel single precision additions. A similar technique is used to design a dual-mode quadruple precision floating-point adder that implements the two-path algorithm. The dual-mode quadruple precision floating-point adder supports one quadruple precision and two parallel double precision additions. To estimate area and worst-case delay, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using the improved single-path and the two-path floating-point addition algorithms. The correctness of all the designs is tested and verified through extensive simulation. Synthesis results show that dual-mode double and dual-mode quadruple precision adders designed with the improved single-path algorithm require roughly 26% more area and 10% more delay than double and quadruple precision adders designed with the same algorithm. Synthesis results obtained for adders designed with the two-path algorithm show that dual-mode double and dual-mode quadruple precision adders requires 33% and 35% more area and 13% and 18% more delay than double and quadruple precision adders, respectively.     

Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy

Some processors designed for consumer applications, such as graphics processing units (CPUs) and the CELL processor, promise outstanding floating-point performance for scientific applications at commodity prices. However, IEEE single precision is the most precise floating-point data type these processors directly support in hardware. Pairs of native floating-point numbers can be used to represent a base result and a residual term to increase accuracy, but the resulting order of magnitude slowdown dramatically reduces the price/performance advantage of these systems. By adding a few simple microarchitectural features, acceptable accuracy can be obtained with relatively little performance penalty. To reduce the cost of native-pair arithmetic, a residual register is used to hold information that would normally have been discarded after each floating-point computation. The residual register dramatically simplifies the code, providing both lower latency and better instruction-level parallelism.     

基于DSP技术和CAN总线的数据采集系统设计

为了满足实验室高性能和分布式数据采集系统的要求,采用浮点DSP芯片设计了嵌入式系统,其硬件系统配备高精度的模拟量输入,具有大容量存储单元,通信单元采用USB接口和CAN总线,系统软件基于状态机的方法设计。使用结果证明,该数据采集系统具有很高的采样精度和快速数据通信功能,在水动力试验中得到成功的应用。     

一种高效结构的多输入浮点加法器在FPGA上的实现

传统的多输入浮点加法运算是通过级联二输入浮点加法器来实现的，这种结构不可避免地使运算时延和所需逻辑资源成倍增加，从而越来越难以满足需要进行高速数字信号处理的需求。本文提出了一种适合在FPGA上实现的浮点数据格式和可以在四级流水线内完成的一种高效多输入浮点加法器结构，并给出了在Xilinx公司Virtex系列芯片上的测试
试数据。     

Parameterized floating-point logarithm and exponential functions for FPGAs

As FPGAs are increasingly being used for floating-point computing, the feasibility of a library of floating-point elementary functions for FPGAs is discussed. An initial implementation of such a library contains parameterized operators for the logarithm and exponential functions. In single precision, those operators use a small fraction of the FPGA’s resources, have a smaller latency than their software equivalent on a high-end processor, and provide about ten times the throughput in pipelined version. Previous work had shown that FPGAs could use massive parallelism to balance the poor performance of their basic floating-point operators compared to the equivalent in processors. As this work shows, when evaluating an elementary function, the flexibility of FPGAs provides much better performance than the processor without even resorting to parallelism. The presented library is freely available from http://www.ens-lyon.fr/LIP/Arenaire/.     

数字高程模型数据的无损数字水印

针对数字高程模型数据（简称DEM数据）提出广义直方图的概念,以DEM数据作为信息承载对象,采用修改广义直方图的方法嵌入水印信息,提取水印时不需要原始数据,水印提取后可完全恢复DEM数据,具有较高的经济价值。此方法计算复杂度低,适宜处理浮点精度的DEM数据,在保证较高峰值性噪比（平均42 dB）的同时嵌入信息量大（≥48.8 KB）,带水印的DEM数据能很好地保持地形形状和起伏特征。