Architectures for wavelet transforms: A survey

Wavelet transforms have proven to be useful tools for several applications, including signal analysis, signal compression and numerical analysis. This paper surveys the VLSI architectures that have been proposed for computing the Discrete and Continuous Wavelet Transforms for 1-D and 2-D signals. The architectures are based upon on-line versions of the wavelet transform algorithms. These architectures support single chip implementations and are optimal with respect to both area and time under the word-serial model.     

2D DWT VLSI architecture for wavelet image processing

A cost-effective VLSI architecture with separate data-paths and their corresponding filter structure is proposed for performing a two-dimensional discrete wavelet transform (2D DWT). Compared with the conventional 2D DWT VLSI architectures, the proposed semi-recursive 2D DWT VLSI architecture has minimum hardware cost, and optimised data-bus utilisation, scheduling control overhead and storage size     

Wavelet transform based novel edge detection algorithms for wideband spectrum sensing in CRNs

The primary task in cognitive radio is to dynamically explore the radio spectrum and reliably detect the co-existing licensed primary transmissions across a wide-band spectrum. This paper focuses on wavelet transform (WT) based wide-band sensing techniques, which identify the edges of the multiple frequency bands simultaneously. Novel edge detection algorithms are proposed based on continuous WT (CWT) and discrete WT (DWT) techniques, applied on wide-band power spectrum. In CWT based spectrum sensing, logarithmic scaling preceded by a thresholding is performed on the CWT coefficients to enhance the small modulus maxima values at the edges, resulting in better detection probability. Since the logarithmic scaling magnifies the spurious edges, the proposed algorithm increases the false alarm probability at high noise variance. To alleviate this problem, DWT based algorithms are proposed, where DWT performs simultaneous denoising and edge detection. To achieve good detection performance at poor SNR scenario, a moving average filtering strategy is adopted at different levels of DWT based algorithms and better performance is achieved even with lower scale value of DWT, thereby reducing the computation time. Comparative studies show that the proposed algorithms outperform the existing WT based edge detection algorithms in the dynamic and frequency selective channels as well.     

From the wavelet series to the discrete wavelet transform-theinitialization

The discrete wavelet transform (DWT) is computed by subband filters bank and often used to approximate wavelet series (WS) and continuous wavelet transform (CWT). The approximation is often inaccurate because of improper initialized discretization of the continuous-time signal. In this correspondence, the problem is analyzed, and two simple algorithms for the initialization are introduced. Finally, numerical examples are presented to show that our algorithms are more effective than others     

基于DSP Builder的二维提升小波变换实现

离散小波变换在图像压缩处理中有着重要的作用,并得到了广泛的应用.与传统的基于卷积的架构相比较,基于提升的架构具有需要较少的硬件资源,占用较少的芯片面积等优点.在DSP Builder中实现了基于提升的一维离散小波变换,并通过构造相关的存储器控制逻辑,完成了二维离散小波变换架构的设计.利用该架构对图像进行离散小波变换,与软件变换的结果相比较,并计算出图像的峰值信噪比,验证了其正确性.     

RNS-FPL merged architectures for orthogonal DWT

Novel, regular, compact and easily scalable residue number system (RNS) field-programmable logic (FPL) merged architectures for the orthogonal 1D discrete wavelet transform (DWT) and 1D inverse discrete wavelet transform (1DWT) are presented. These structures halve the number of look-up tables (LUTs) required per octave, providing a sustained throughput independent of the input data and filter coefficient precision. They are suitable to be considered as the core of 2D DWT processors for high data rate image processing applications     

二维离散小波变换的VLSI实现

小波变换图像编码获得了比传统DCT变换编码更好的图像质量和更高的压缩比,然而,实时二维小波变换需要大量运算,因此,专用小波变换芯片的设计已成为小波图像编码中的关键技术,文章提出了一种高速的二维小波变换的VLSI结构。根据模块化的设计思想,设计出一组二维小波变换的基本模块。通过将这些模块按变换要求适当组装,完成了多级二维小波变换,编写了相应的VerilogHDL模型,并进行了仿真和逻辑综合。     

Performance comparison of two-dimensional discrete wavelet transform computation schedules on a VLIW digital signal processor

The two-dimensional discrete wavelet transform (2D DWT) is becoming one of the standard tools for image and video compression systems. Various input-traversal schedules have been proposed for its computation. Here, major schedules for 2D DWT computation are compared with respect to their performance on a very long instruction-word (VLIW) digital signal processor (DSP). In particular, three popular transform-production schedules are considered: the row-column, the line based and the block based. Realisations of the wavelet transform according to the considered schedules have been developed. They are parameterised with respect to filter pair, image size and number of decomposition levels. All realisations have been mapped on a VLIW DSP, as these processors currently form an attractive alternative for the realisation of signal, image and video processing systems. Performance metrics for the realisations for a complete set of parameters have been obtained and compared. The experimental results show that each realisation performs better for different points of the parameter space.     

Analog wavelet transform using multiple-loop feedback switched-current filters and simulated annealing algorithms

A new approach for implementing continuous wavelet transform (CWT) based on multiple-loop feedback (MLF) switched-current (SI) filters and simulated annealing algorithms (SAA) is presented. First, the approximation function of wavelet bases is performed by employing SAA. This approach allows for the circuit implementation of any other wavelets. Then the wavelet filter whose impulse response is the wavelet approximation function is designed using MLF architectures, which is constructed with SI differentiators and multi-output cascade current source circuits. Finally, the CWT is implemented by controlling the clock frequency of wavelet filter banks. Simulation results of the proposed circuits and the filter banks show the advantages of such new designs.     

Time-domain design of low delay wavelet transforms

The authors use a time-domain design methodology previously used for perfect reconstruction filter banks to design wavelet prototypes which may be used to generate the discrete wavelet transform (DWT). An advantage of this method is the significant reduction in the inherent delay, and consequent reduction in the number of multiplications required to implement the DWT. It is proposed that these low delay wavelets will find applications in time critical systems.<>     

Scalability of 2-D wavelet transform algorithms: analytical and experimental results on MPPs

This paper studies the scalability of two-dimensional (2-D) discrete wavelet transform (DWT) algorithms on massively parallel processors (MPPs). The principal operation in the 2-D DWT is the filtering operation used to implement the filter banks of the 2-D subband decomposition. This filtering operation can be implemented as a convolution in the time domain or as a multiplication in the frequency domain. We demonstrate that there exist combinations of machine size, image size, and wavelet kernel size for which the time-domain algorithms outperform the frequency domain algorithms and vice-versa. We therefore demonstrate that a hybrid approach that combines time- and frequency-domain approaches can yield linear scalability for a broad range of problem and machine sizes. Furthermore, we show the effect of processor speed versus communication overhead and the use of separable versus nonseparable wavelets on the crossover points between the algorithm approaches.     

Memory-Efficient and High-Speed VLSI Implementation of Two-Dimensional Discrete Wavelet Transform Using Decomposed Lifting Scheme

Novel decomposed lifting scheme (DLS) is presented to perform one-dimensional (1D) discrete wavelet transform (DWT) with consistent data flow in both row and column dimension. Based on the proposed DLS, intermediate data can be transferred seamlessly between the column processor and the row processor in the hardware implementation of two-dimensional (2D) DWT, resulting in the reduction of on-chip memory, output latency and control complexity. Moreover, the implementation of 2D DWT can be easily extended to achieve higher processing speed with controlled increase of hardware cost. Memory-efficient and high-speed architectures are proposed to implement 2D DWT for JPEG2000, which are called fast architecture (FA) and high-speed architecture (HA). FA and HA can perform 2D DWT in N ² /2 and N ² /4 clock cycles for an N×N image, respectively, but the required internal memory is only 4N for 9/7 DWT and 2N for 5/3 DWT. Compared with the works reported in previous literature, the proposed designs provide excellent performance in hardware cost, control complexity, output latency and computing time. The proposed designs were implemented to process 2D 9/7 DWT in SMIC 0.18 μm CMOS logic fabrication with 4 KB internal memory for the image size 512 × 512. The areas are only 999137 um ² and 1333054 um ² for FA and HA, respectively, but the operation frequency can be up to 150 MHz.     

On the Dual-Tree Complex Wavelet Packet and $M$-Band Transforms

The two-band discrete wavelet transform (DWT) provides an octave-band analysis in the frequency domain, but this might not be ldquooptimalrdquo for a given signal. The discrete wavelet packet transform (DWPT) provides a dictionary of bases over which one can search for an optimal representation (without constraining the analysis to an octave-band one) for the signal at hand. However, it is well known that both the DWT and the DWPT are shift-varying. Also, when these transforms are extended to 2-D and higher dimensions using tensor products, they do not provide a geometrically oriented analysis. The dual-tree complex wavelet transform , introduced by Kingsbury, is approximately shift-invariant and provides directional analysis in 2-D and higher dimensions. In this paper, we propose a method to implement a dual-tree complex wavelet packet transform , extending the as the DWPT extends the DWT. To find the best complex wavelet packet frame for a given signal, we adapt the basis selection algorithm by Coifman and Wickerhauser, providing a solution to the basis selection problem for the . Lastly, we show how to extend the two-band to an -band (provided that ) using the same method.     

小波图像编码的VLSI实现

设计了一种模块化的二维离散小波变换(2-D DWT)的VLSI结构.该结构可以实时完成小波变换,且很容易扩展.针对零树编码硬件实现方面的不足,利用一种简单的顺序扫描方式和两个标志阵列,设计了一种适合硬件实现的快速零树编码算法(FZIC)和FZIC硬件实现的VLSI结构,编写了2-D DWT和FZIC硬件结构的Veri log HDL模型,并进行了仿真和逻辑综合.结合2-D DWT和FZIC,实现了小波图像编码系统 ,并用ALTERA CPLD成功进行了验证.     

The recursive pyramid algorithm for the discrete wavelet transform

The recursive pyramid algorithm (RPA) is a reformulation of the classical pyramid algorithm (PA) for computing the discrete wavelet transform (DWT). The RPA computes the N-point DWT in real time (running DWT) using just L(log N-1) words of storage, as compared with O(N) words required by the PA. L is the length of the wavelet filter. The RPA is combined with the short-length FIR filter algorithms to reduce the number of multiplications and additions     

CCSDS中二维整数小波变换的FPGA实现方法

CCSDS空间图像压缩标准(CCSDS 122.0-B-1)的核心算法之一是三级二维小波变换,此变换适合用可编程逻辑电路实现。文章介绍了整数9/7小波变换的特点,提出了一种基于FPGA的二维变换快速实现结构,该方法利用FPGA内部Block RAM进行行暂存,实现了行列同时变换的效果,节省了内部寄存器资源,并获得了较高的数据吞吐率。在此基础上,文章还给出了两种适用于不同需求的多级变换架构,并通过仿真验证了其合理性。     

二维9／7小波变换VLSI设计

为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散9／7小波变换（DWT）Mesh结构的VLSI设计方案,利用这种Mesh结构的VLSI能够实现并行处理一个图像的所有像素点。这种并行处理的Mesh结构可提高小渡变换电路速度,以及图像压缩的速度。     

Three-dimensional discrete wavelet transform architectures

The three-dimensional (3-D) discrete wavelet transform (DWT) suits compression applications well, allowing for better compression on 3-D data as compared with two-dimensional (2-D) methods. This paper describes two architectures for the 3-D DWT, called the 3DW-I and the 3DW-II. The first architecture (3DW-I) is based on folding, whereas the 3DW-II architecture is block-based. Potential applications for these architectures include high definition television (HDTV) and medical data compression, such as magnetic resonance imaging (MRI). The 3DW-I architecture is an implementation of the 3-D DWT similar to folded 1-D and 2-D designs. It allows even distribution of the processing load onto 3 sets of filters, with each set performing the calculations for one dimension. The control for this design is very simple, since the data are operated on in a row-column-slice fashion. Due to pipelining, all filters are utilized 100% of the time, except for the start up and wind-down times. The 3DW-II architecture uses block inputs to reduce the requirement of on-chip memory. It has a central control unit to select which coefficients to pass on to the lowpass and highpass filters. The memory on the chip will be small compared with the input size since it depends solely on the filter sizes. The 3DW-I and 3DW-II architectures are compared according to memory requirements, number of clock cycles, and processing of frames per second. The two architectures described are the first 3-D DWT architectures     

双树复小波变换及其应用综述

双树复小波变换是为克服通常的离散小波变换的缺陷而提出的。当对应小波基（近似）满足Hilbert变换关系时，双树复小波变换能够极大地减小通常的实小波变换中的平移敏感性，改善方向选择性。这些优点使双树复小波变换成为有效的图像配准融合工具，能够显著提高配准融合质量。     

Efficient architectures for two-dimensional discrete wavelet transform using lifting scheme.

Novel architectures for 1-D and 2-D discrete wavelet transform (DWT) by using lifting schemes are presented in this paper. An embedded decimation technique is exploited to optimize the architecture for 1-D DWT, which is designed to receive an input and generate an output with the low- and high-frequency components of original data being available alternately. Based on this 1-D DWT architecture, an efficient line-based architecture for 2-D DWT is further proposed by employing parallel and pipeline techniques, which is mainly composed of two horizontal filter modules and one vertical filter module, working in parallel and pipeline fashion with 100% hardware utilization. This 2-D architecture is called fast architecture (FA) that can perform J levels of decomposition for N * N image in approximately 2N2(1 - 4(-J))/3 internal clock cycles. Moreover, another efficient generic line-based 2-D architecture is proposed by exploiting the parallelism among four subband transforms in lifting-based 2-D DWT, which can perform J levels of decomposition for N * N image in approximately N2(1 - 4(-J))/3 internal clock cycles; hence, it is called high-speed architecture. The throughput rate of the latter is increased by two times when comparing with the former 2-D architecture, but only less additional hardware cost is added. Compared with the works reported in previous literature, the proposed architectures for 2-D DWT are efficient alternatives in tradeoff among hardware cost, throughput rate, output latency and control complexity, etc.