Multilevel characteristics and operating mechanisms of nonvolatile memory devices based on a floating gate of graphene oxide sheets sandwiched between two polystyrene layers

Nonvolatile organic memory devices were fabricated utilizing a graphene oxide (GO) layer embedded between two polystyrene (PS) layers. Scanning electron microscope images of GO sheets sandwiched between two PS layers showed that the GO sheets were clearly embedded in the PS layers. Capacitance–voltage (C–V) curves of the Al/PS/GO/PS/n-type Si devices clearly showed hysteresis behaviors with multilevel characteristics. The window margin of the nonvolatile memory devices increased from 1 to 7 V with increasing applied sweep voltages from 6 to 32 V. The cycling retention of the ON/OFF switching for the devices was measured by applying voltages between +15 and −15 V. While the capacitance of the memory devices at an ON state have retained as 230 pF up to 10⁴ cycles, that at an OFF state maintained as 16 pF during three times of repeated measurements. The extrapolation of the retention data for the devices maintained up to 10⁶ cycles. The operating mechanisms of the nonvolatile organic memory devices with a floating gate were described by the C–V results and the energy band diagrams.     

Frequency and voltage dependency of interface states and series resistance in Al/SiO2/p-Si MOS structure

The capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of Al/SiO₂/p-Si metal-oxide-semiconductor (MOS) Schottky diodes have been measured in the voltage range from ?3 to +3 V and frequency range from 5 KHz to 1 MHz at room temperature. It is found that both C and G/ω of the MOS capacitor are very sensitive to frequency. The fairly large frequency dispersion of C–V and G/ω–V characteristics can be interpreted in terms of the particular distribution of interface states at SiO₂/Si interface and the effect of series resistance. At relatively low frequencies, the interface states can follow an alternating current (AC) signal that contributes to excess capacitance and conductance. This leads to an anomalous peak of C–V curve in the depletion and accumulation regions. In addition, a peak at approximately ?0.2 V appears in the R_s–V profiles at low frequency. The peak values of the capacitance and conductance decrease with increasing frequency. The density distribution profile of interface state density (N_ss) obtained from C_HF–C_LF capacitance measurement also shows a peak in the depletion region.     

Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal–ferroelectric–oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO₂/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C–V memory window was 6 V for metal–ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25 V for MFeOS capacitors with a buffer layer of 2.5 and 5 nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO₂ buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.     

Nonvolatile memory and opto-electrical characteristics of organic memory devices with zinc oxide nanoparticles embedded in the tris(8-hydroxyquinolinato)aluminum light-emitting layer

The nonvolatile organic memory devices based on the tris(8-hydroxyquinolinato)aluminum (Alq₃) emitting layer embedded with zinc oxide nanoparticles (ZnO-NPs) are reported. The devices have a typical tri-layer structure consisting of the Alq₃/ZnO-NPs/Alq₃ layers interposed between indium tin oxide (ITO) and aluminum (Al) electrodes. An external bias is used to program the ON and OFF states of the device that are separated by a four-orders-of-magnitude difference in conductivity. No significant degradation of the device is observed in either the ON or OFF state after continuous stress (∼10⁵ s) and multicycle (∼10³ cycles) testings. These nanoparticles behave as the charge trapping units, which enable the nonvolatile electrical bistability when biased to a sufficiently high voltage. Impedance spectroscopy, capacitance–voltage (C–V) and current–voltage (I–V) analysis are used to verify the possible physical mechanism of the switching operation. Moreover, it is found that the location of the ZnO-NPs could affect the memory and opto-electrical characteristics of the devices, such as the ON/OFF ratio, threshold voltage and turn-on voltage, which can be attributed to the influence of the ZnO-NPs and diffused Al atoms in the bulk of the Alq₃ layer.     

Memory effects in hybrid silicon-metallic nanoparticle-organic thin film structures

We report on the electrical behaviour of metal–insulator–semiconductor (MIS) structures fabricated on silicon substrates and using organic thin films as the dielectric layers. These insulating thin films were produced by different methods, including spin-coating (polymethylmethacrylate), thermal evaporation (pentacene) and Langmuir–Blodgett deposition (cadmium arachidate). Gold nanoparticles, deposited at room temperature by chemical self-assembly, were used as charge storage elements. In all cases, the MIS devices containing the nanoparticles exhibited hysteresis in their capacitance versus voltage characteristics, with a memory window depending on the range of the voltage sweep. This hysteresis was attributed to the charging and discharging of the nanoparticles from the gate electrode. A maximum memory window of 2.5 V was achieved by scanning the applied voltage of an Al/pentacene/Au nanoparticle/SiO₂/p-Si structure between 9 and −9 V.     

Electrical and photoelectrical characterization of an organic–inorganic heterojunction based on quinoline yellow dye

An organic–inorganic contact was fabricated by forming a thin film of quinoline yellow dye (QY) on a p-Si wafer and evaporating Al metal on the film. The current–voltage (I–V) and capacitance–voltage (C–V) measurements of Al/QY/p-Si heterostructure were applied in dark and room temperature to calculate the characteristic parameters of diode like ideality factor, barrier height and series resistance. Ideality factor and barrier height values were found as 1.23 and 0.87 eV from I–V data, respectively. The series resistance value of the device was determined as 1.8 kΩ by using modified Norde function. The C–V measurements were carried out at different frequencies and it was seen that capacitance value decreased with increasing frequency. Interface state density distribution was calculated by means of I–V measurement. In addition the optical absorption of thin QY film on glass was measured and optical band gap of the film was found as 2.73 eV. Furthermore, I–V measurements of Al/QY/p-Si/Al were taken under illumination between 40 and 100 mW/cm². It was observed that reverse bias current of the device increased with light intensity. Thus, the heterojunction had a strong response to the light and it can be suitable for electrical and optoelectronic applications like a photodiode.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

The source of negative capacitance and anomalous peak in the forward bias capacitance-voltage in Cr/p-si Schottky barrier diodes (SBDs)

The frequency and voltage dependence of capacitance–voltage (C–V) and conductance-voltage (G/ω−V) characteristics of the Cr/p-Si metal semiconductor (MS) Schottky barrier diodes (SBDs) were investigated in the frequency and applied bias voltage ranges of 10 kHz to 5 MHz and (−4 V)−(+4 V), respectively, at room temperature. The effects of series resistance (R_s) and density distribution of interface states (N_ss), both on C–V and G/ω−V characteristics were examined in detail. It was found that capacitance and conductance, both, are strong functions of frequency and applied bias voltage. In addition, both a strong negative capacitance (NC) and an anomalous peak behavior were observed in the forward bias C–V plots for each frequency. Contrary to the behavior of capacitance, conductance increased with the increasing applied bias voltage and there happened a rapid increase in conductance in the accumulation region for each frequency. The extra-large NC in SBD is a result of the existence of R_s, N_ss and interfacial layer (native or deposited). In addition, to explain the NC behavior in the forward bias region, we drew the C–I and G/ω−I plots for various frequencies at the same bias voltage. The values of C decrease with increasing frequency at forward bias voltages and this decrease in the NC corresponds to an increase in conductance. The values of N_ss were obtained using a Hill–Coleman method for each frequency and it exhibited a peak behavior at about 30 kHz. The voltage dependent profile of R_s was also obtained using a Nicollian and Brews methods.     

Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications

Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO_xN_y metal oxide NPs embedded in the HfO_xN_y high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O₂/N₂ ambient. Well-isolated TiO_xN_y NPs with a diameter of 5–20 nm, a surface density of ～3 × 10¹¹ cm^?2, and a charge trap density of around 2.33 × 10¹² cm^?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping.     

Flexible and transparent nanocrystal floating gate memory devices using silk protein

The charge storage behavior of a floating gate memory device using carbon nanotube-CdS nanostructures embedded in Bombyx mori silk protein matrix has been demonstrated. The capacitance – voltage characteristics in ITO/CNT–CdS-silk composite/Al device exhibits a clockwise hysteresis behavior due to the injection and storage of holes in the quantized valence band energy levels of CdS nanocrystals. The enhanced charge injection resulting in increase in memory window is observed at higher sweeping voltages. Nearly frequency independent hysteresis width over a wide range of 100 kHz–2.0 MHz, indicates its origin due to the charge storage in nanocrystals. The memory behavior of carbon nanotube–CdS nanostructures/silk nanocomposite devices has also been demonstrated on polyethylene terephthalate substrates, which may provide the way for flexible, transparent and printable electronic devices.     

ZnO/p-Si heterojunction photodiode by sol–gel deposition of nanostructure n-ZnO film on p-Si substrate

The electrical and photovoltaic properties of the nanostructure ZnO/p-Si diode have been investigated. The nanostructure ZnO/p-Si diode was fabricated using sol–gel spin coating method. The ideality factor and barrier height of the diode were found to be 3.18 and 0.78 eV, respectively. The obtained n ideality factor is higher than 2, indicating that the diode exhibits a non-ideal behavior due to the oxide layer and the presence of surface states. The nanostructure of the ZnO improves the quality of ZnO/p-Si interface. The diode shows a photovoltaic behavior with a maximum open circuit voltage V_oc of 0.26 V and short-circuits current I_sc of 1.87×10^?8 A under 100 mW/cm². It is evaluated that the nanostructure ZnO/p-Si diode is a photodiode with the obtained electronic parameters.     

Interface states in polyfluorene-based metal–insulator–semiconductor devices

Hybrid metal–insulator–semiconductor structures based on ethyl-hexyl substituted polyfluorene (PF2/6) as the active polymer semiconductor were fabricated on a highly doped p-Si substrate with Al₂O₃ as the insulating oxide layer. We present detailed frequency-dependent capacitance–voltage (C–V) and conductance–voltage characteristics of the semiconductor/insulator interface. PF2/6 undergoes a transition to an ordered crystalline phase upon thermal cycling from its nematic-liquid crystalline phase, confirmed by our atomic force microscope images. Thermal cycling of the PF2/6 films significantly improves the quality of the (PF2/6)/Al₂O₃ interface, which is identified as a reduced hysteresis in the C–V curve and a decreased interface state density (D_it) from ∼3.9 × 10¹² eV⁻¹ cm⁻² to ∼3.3 × 10¹¹ eV⁻¹ cm⁻² at the flat-band voltage. Interface states give rise to energy levels that are confined to the polymer/insulator interface. A conductance loss peak, observed due to the capture and emission of carriers by the interface states, fits very well with a single time constant model from which the D_it values are inferred.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

Influence of electrical field dependent depletion at metal–polymer junctions on resistive switching of poly(N-vinylcarbazole) (PVK)-based memory devices

Polymer memory devices using Au nanoparticles (Au NPs) incorporated poly(N-vinylcarbazole) (PVK) as the active layer and Al films as the electrodes are investigated. The Al/PVK:Au NPs/Al devices exhibit electrical bistability in the I–V characteristics and show a conductance difference ratio between the high-resistance state (HRS) and low-resistance state (LRS) by a factor of 10⁵. Furthermore, the Au nanoparticle/PVK hybrid memory device can be programmed and exhibits excellent thermal stability up to 154 °C in ambient atmosphere. The current conduction is dominated by Schottky emission at HRS and exhibits Ohmic behavior at LRS. The dependence of the current conduction on temperature reveals the connection between the conduction character and the energy-band offsets at the metal (Al or Au)–PVK junctions. In addition, the resistive switching is correlated with the width of depletion region in PVK, which varies with the change of hole carrier concentration upon applying electrical field.     

Characteristics of RF reactive sputter-deposited Pt/SiO2/n-InGaN MOS Schottky diodes

All RF sputtering-deposited Pt/SiO₂/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO_2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (I–V) and capacitance–voltage (C–V) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (I–V) and 0.82 eV (C–V) after annealing at 400 °C for 15 min in N₂ ambient, compared to that of 0.67 eV (I–V) and 0.79 eV (C–V) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10⁻⁷ A for the as-deposited to 1.4×10⁻⁷ A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (R_s) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by C–V measurement.     

Study of blocking effect of Cu-phthalocyanine layer in zinc oxide/pentacene/CuPc/C60/Al organic solar cells by electric field-induced optical second harmonic generation measurement

By employing electric-field-induced optical second-harmonic generation (EFISHG) measurement, we studied the blocking effect of sandwiched Cu-phthalocyanine (CuPc) layer on IZO/pentacene/Cu-phthalocyanine (CuPc)/C₆₀/Al organic solar cells (OSCs). Results evidently showed that the Maxwell–Wagner type interfacial charging appears at both pentacene/CuPc and CuPc/C₆₀ interfaces, depending on the CuPc layer thickness. When the thickness of CuPc layer was 8 nm, the charging at the two interfaces was significantly suppressed and the I–V characteristic was improved. CuPc layer is available as a blocking layer for the regulation of interfacial charging induced in IZO/pentacene/C₆₀/Al organic solar cells (OSCs). The blocking effect of the CuPc layer was discussed on the basis of Maxwell–Wagner model analysis.     

Using metal/organic junction engineering to prepare an efficient organic base-modulation triode and its inverter

In this study, we investigated the influence of a buffer layer of molybdic oxide (MoO₃) at the metal/organic junction on the behavior of organic base-modulation triodes. The performance of devices featuring MoO₃/Al as the emitter electrode was enhanced relative to that of corresponding devices with Au and Ag, presumably because of the reduced in the contact barrier and the prevention of metal diffusion into the organic layer. The device exhibited an output current of ?16.1 μA at V_B = ?5 V and a current ON/OFF ratio of 10³. Using this architecture, we constructed resistance–load inverters that exhibited a calculated gain of 6.     

Properties of high sensitivity ZnO surface acoustic wave sensors on SiO2/(1 0 0) Si substrates

The properties of ZnO/SiO₂/Si surface acoustic wave (SAW) Love mode sensors were examined and optimized to achieve high mass sensitivity. SAW devices A and B, were designed and fabricated to operate at resonant frequencies around 0.7 and 1.5 GHz. The ZnO films grown by pulsed laser deposition on SiO₂/Si demonstrated c-axis growth and the fabricated devices showed guided shear horizontal surface acoustic wave (or Love mode) propagation. Acoustic phase velocity in the ZnO layer was measured in both devices A and B and theoretical and experimental evaluation of the mass sensitivity showed that the maximum sensitivity is obtained for devices with ZnO guiding layer thicknesses of 340 nm and 160 nm for devices A and B, respectively. The performance of the SAW sensors was validated by measuring the mass of a well-characterized polystyrene–polyacrylic acid diblock copolymer film. For the optimized sensors, maximum mass sensitivity values were as high as 4.309 μm²/pg for device A operating at 0.7477 GHz, and 8.643 μm²/pg for device B operating at 1.5860 GHz. The sensors demonstrated large frequency shifts per applied mass (0.1–4 MHz), excellent linearity, and extended range in the femto-gram region. The large frequency shifts indicated that these sensors have the potential to measure mass two to three orders of magnitude lower in the atto-gram range.     

Sol–gel synthesized Titania nanoparticles deposited on porous polycrystalline silicon: Improved carbon dioxide sensor properties

Titania nanoparticles (TNPs) were synthesized by a sol–gel method in our laboratory using titanium tetrachloride as the precursor and isopropanol as the solvent. The particles׳ size distribution histogram was determined using ImageJ software and the size of TNPs was obtained in the range of 7.5–10.5 nm. The nanoparticle with the average size of 8.5 nm was calculated using Scherrer׳s formula. Homogeneous and spherical nanoparticles were characterized by X-ray diffraction (XRD), atomic force microscopy (AFM), field emission scanning electron microscopy (FESEM) and UV–visible spectroscopy (UV–vis). The X-ray powder diffraction analysis showed that the prepared sample (TNPs) has pure anatase phase. TNPs were deposited on porous polycrystalline silicon (PPS) substrate by electron beam evaporation. The TNPs thickness was 23±2 nm at 10⁻⁵ mbar pressure at room temperature. Porosity was performed by an anodization method. Since polycrystalline silicon wafers consist of different grains with different orientations, the pore size distribution in porous layer is non-uniform [1]. Therefore, the average diameter of pores can be reported in PPS layer analysis. Average diameter of pores was estimated in the range of 5 μm which was characterized by FESEM. The nanostructured thin films devices (Al/Si/PPS/TNPs/Al and Al/Si/PPS/Al) were fabricated in the sandwich form by aluminum (Al) electrodes which were also deposited by electron beam evaporation. Electrical measurements (I–V curves) demonstrated the semiconducting behavior of thin film devices. The gas sensitivity was studied on exposure to 10% CO₂ gas. As a result, conductivity of devices increased on exposure to CO₂ gas. The device with TNPs thin film (Al/Si/PPS/TNPs/Al) was more sensitive and, had better response and reversibility in comparison with the device without TNPs thin film (Al/Si/PPS/Al).     

Fabrication,temperature dependent current-voltage characteristics and photoresponse properties of Au/α-PbO2/p-Si/Al heterojunction photodiode

Thin film of lead dioxide, α-PbO₂, has been grown by thermal evaporation technique on the single crystal of p-Si substrate and heterojunction photodiode, Au/α-PbO₂/p-Si/Al, was fabricated. The current-voltage characteristics of the diode have been studied in the temperature ranged from 303 to 373 K and the voltage applied during measurements varied from −1 to 1.5 V. It was found from the (I-V) characteristics of the diode that the conduction mechanisms in the forward bias direction are controlled by the thermionic emission at bias potential ≤0.7 V followed by single trap space charge limited current (SCLC) conduction in the voltage range >0.7 V. The capacitance-voltage characteristics of the device were studied at room temperature in dark condition and it has been shown that the diode is abrupt junction. The carrier concentration on both sides of the depletion layer has been determined. Energy band diagram for α-PbO₂/p-Si device was constructed. The device under illumination with light of intensity 20 W/m² gives acceptable values of photoresponse parameters such as photosensitivity and photoconductivity. The presented photodiode parameters exhibit the typical photosensor applications with reproducibility phenomenon.