同时同频全双工LTE射频自干扰抑制能力分析及实验验证

同时同频全双工本地发射信号会对本地接收信号产生强自干扰,为了使信号能够通过射频接收通道及模数转换器件,需要在射频前端进行自干扰抑制。在自干扰为直射路径的条件下,该文采用直接射频耦合法,对长期演进(LTE)同时同频全双工自干扰抑制进行实验测试;分析推导了自干扰功率、带宽及线缆、幅度、相位调整误差对射频自干扰抑制能力的影响;得到了射频自干扰抑制能力的闭合表达式。分析表明对于20 MHz带宽,-10 dBm接收功率的LTE射频自干扰信号,理论上能抑制54 dB的射频自干扰,而实验测试结果表明能抑制51.2 dB。     

箕舌线变步长LMS/F算法数字域自干扰消除研究北大核心CSCD

自干扰消除技术是实现带内全双工(IBFD)通信的重要前提,其中数字域自干扰消除是带内全双工通信系统中硬件复杂度最低、灵活性最高的自干扰消除技术,并且是自干扰消除的最后一道防线。然而,其消除能力仍需提升,主要是如何处理收敛速度和稳态精度之间的平衡,并且还要具备突变信道的自适应能力。文章提出了一种新的全双工系统的数字自干扰消除方法,发射链路采用数字、模拟预失真技术消除功率放大器的非线性失真,使用辅助接收链获取发射链路信号副本,在数字域中利用重构自干扰信号副本消除接收信号残余自干扰信号和功率放大器残余非线性失真,并通过在接收链与辅助接收链之间共用一个振荡器消除部分接收机相位噪声。仿真表明,该方法与已有变步长LMS消除方法相比,在信噪比为5 dB的条件下,能够在提高收敛速度的同时获得优于变步长LMS方法的消除能力。     

基于小型化模块相位噪声的间接测试方法

收发电路模块的本振信号质量对系统的整体性能有重要影响。小型化模块由于尺寸的限制,无法在本振的输出端设置测试端口,因此无法直接在本振的输出端准确地测试相位噪声。提出了一种针对小型化收发电路模块本振信号相位噪声的间接测试方法,该方法需要测试模块的输入/输出信号的功率、相位噪声以及整个收发通路的增益和噪声系数,通过公式计算得到本振信号的相位噪声。采用此方法对小型化收发电路模块进行测试,将得到的相位噪声结果与器件指标进行对比,两者高度一致,从而验证了间接测试方法的正确性和有效性。     

一种宽带多通道合成孔径雷达系统幅相特性测量与校正方法

多通道技术可以用来提高系统的频带宽度,是实现分辨率优于0.1 m的超高分辨率机载合成孔径雷达(SAR)系统的一种有效的技术途径。该文针对实际雷达系统中采用的单通道宽带信号发射、8通道下变频接收来完成宽带信号收发的方案,提出一种对该收发系统的幅相误差进行测量和校正的方法,该方法采用空间闭环辐射提取宽带收发通道的幅相误差,采取具有频偏误差修正的矢量网络分析技术完成多通道接收单元中各子通道幅相误差的提取,将两者结合用于补偿整个系统误差对信号合成和成像处理所带来的影响。实际测试数据和外场飞行试验结果验证了该系统测量和校正方法的有效性和可行性。     

激光相干雷达中光单次下变频技术

在相干激光雷达远程测距中,为提高雷达的探测距离和距离分辨力,通常使用大时宽带宽积的信号如调频信号对光载波进行调制,并在接收端进行脉冲压缩处理,为降低接收端数字信号处理的数据量以提高运算的实时性,需要将接收信号下变频至合适的频段。传统的外差式雷达接收机需对光信号和电信号分别进行一次下变频,导致系统结构较复杂,且受器件非理想化的限制,下变频过程中会引入额外的噪声,此外还存在镜像频率噪声干扰的问题,导致解调信号信噪比降低。提出了一种将光信号直接下变频至脉冲压缩所需频段的方案,该方案使用正交解调的方式进行,能够简化系统结构同时抑制镜频噪声。首先将本振光进行频移并分为两束,通过控制相位使两本振光相互正交。将信号光分为两束并分别与两路本振光在光电探测器表面进行混频,接着对电信号进行采集,通过相关算法对幅相不平衡进行矫正。经仿真和实验,该方法能够在有效简化激光相干雷达接收机系统结构的同时避免镜频噪声干扰,在10 GSps采样率下,相较于外差式接收机,解调信号信噪比提高了约3 dB。     

一种引入相位补偿的直接时延估计算法

在多天线信号合成技术中,合成系统需在中频完成各信号间时延差估计与补偿,以便进行信号合成,提高接收质量。分析发现,利用同一本振对两路信号下变频会引入新的相差,该相差将导致直接时延估计算法性能下降。通过在直接时延估计算法(ETDE)基础上增加一个相位补偿因子,将时延与相差进行解耦,利用相位补偿因子来修正相差,最终实现无偏时延估计。理论分析与仿真结果均表明,该算法能够不受相差的影响准确估计时延并进行跟踪,相比无相差下的直接时延估计算法,该算法的收敛速度提升1+3(ω/π)2 倍,并且估计性能改善3 dB以上。     

一种多通道雷达接收机数字相位补偿方法

本文针对目前多通道雷达体制中出现的通道相位不一致的情况,提出了一种在中频下变频阶段,利用数字相关算法完成相位一致性补偿的方法。该方法可实时对多通道相位进行调整,补偿精度高,灵活性强,有效的保证了各路信号相位的一致性。     

相位噪声对PSK系统性能的影响

在介绍相位噪声定义的基础上,分析了相移键控(PSK)接收系统的本振信号源相位噪声对误码率的影响.以QPSK调制方式为例,仿真了相位噪声对系统误码率影响,结果证明了接收系统中本振信号源相位噪声的重要性.以实际工程中使用的本振信号源为例,推导了相位噪声和信号抖动所导致的BPSK和QPSK接收系统信噪比的限制.理论分析与工程...     

Ku波段收发组件设计分析

该Ku波段收发组件包括发射双通道上变频和接收下变频两部分内容。双通道上变频模块包括本振、上变频器、滤波器、放大器、耦合器、隔离器、开关等。双通道上变频模块的发射通路具有耦合输出,可以接到接收通道耦合输入,用来形成发射通道与接收通道的自闭环,完成系统自检测试功能。下变频通道前端主要由低噪声放大器、耦合器、混频器以及中频滤波和放大器组成。     

一种应用于WLAN相位可调的本振缓冲器

该文提出了一种应用于WLAN相位可调的本振缓冲器,用于校准直接下变频收发机的I/Q两路不平衡。该电路通过开关输入MOS管源极的电容阵列,延迟本振信号,从而调节信号的相位。该文采用SMIC 0.18m工艺实现了4.8~6GHz的I/Q两路本振缓冲器的设计,其版图面积为650550m2。仿真结果表明,在5位控制字作用下,I或者Q路本振缓冲器的相移在0~8的范围内呈现近乎线性的变化,而本振缓冲器的输出功率的变化范围只有0.2dB。     

An efficient RAKE receiver architecture with pilot signalcancellation for downlink communications in DS-CDMA indoor wirelessnetworks

This paper deals with a RAKE receiver architecture which makes use of a pilot signal broadcast by the base station to obtain channel parameter estimates in a direct-sequence code division multiple access (DS-CDMA) indoor wireless network. A suitable cancellation algorithm, which is different from previous approaches, is used to reduce multipath interference due to the pilot signal. Numerical results are used to demonstrate the performance of the proposed RAKE receiver in terms of the bit error probability under typical multipath fading propagation conditions. Performance comparisons with the ideal case of perfect channel parameter estimation are given in order to highlight the good behavior of the proposed approach     

Network Lifetime Enhancement of Wireless Sensor Networks Using EFRP Protocol

This paper presents a novel transceiver architecture for in-band full duplex radio. A transceiver for full duplex radio requires a self-interference (SI) canceler to remove the SI occurring from the transmitter to the receiver, and a full duplex transceiver generally has two SI cancelers: one at the analog RF stage and the other at the baseband stage. The output from the SI canceler at the RF stage includes much residual SI, and it decreases the number of bits allocated to the analog baseband signal at the analog-to-digital converter. A 1-tap analog baseband SI canceler that uses a replica signal including only the direct path component of the residual SI has been presented for preventing degradation. However, the architecture cannot remove the SI well due to the high Ricial K-factor. To address the problem, the presented architecture has an SI canceler at the analog baseband stage, and this canceler employs a replica signal that is output from a digital-to-analog converter. Because the replica signal is generated in the digital domain, the architecture can generate a multipath replica signal, and improved performance can be expected. Numerical and theoretical analyses are shown to validate the effectiveness of the presented architecture.

     

Full‐Duplex Operations in Wireless Powered Communication Networks

In this paper, a wireless powered communication network (WPCN) consisting of a hybrid access point (H‐AP) and multiple user equipment (UE), all of which operate in full‐duplex (FD), is described. We first propose a transceiver structure that enables FD operation of each UE to simultaneously receive energy in the downlink (DL) and transmit information in the uplink (UL). We then provide an energy usage model in the proposed UE transceiver that accounts for the energy leakage from the transmit chain to the receive chain. It is shown that the throughput of an FD WPCN using the proposed FD UE (FD‐WPCN‐FD) can be maximized by optimal allocation of the UL transmission time to the UE by solving a convex optimization problem. Simulation results reveal that the use of the proposed FD UE efficiently improves the throughput of a WPCN with a practical self‐interference cancellation capability at the H‐AP. Compared to the WPCN with FD H‐AP and half‐duplex (HD) UE, FD‐WPCN‐FD achieved an 18% throughput gain. In addition, the throughput of FD‐WPCN‐FD was shown to be 25% greater than that of WPCN in which an H‐AP and UE operated in HD.     

A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.     

Polarization-based optimal detection scheme for digital self-interference cancellation in full-duplex system

In order to detect and cancel the self-interference (SI) signal from desired binary phase-shift keying (BPSK) signal, the polarization-based optimal detection (POD) scheme for cancellation of digital SI in a full-duplex (FD) system is proposed. The POD scheme exploits the polarization domain to isolate the desired signal from the SI signal and then cancel the SI to obtain the interference-free desired signal at the receiver. In FD communication, after antenna and analog cancellation, the receiver still contains residual SI due to non-linearities of hardware imperfections. In POD scheme, a likelihood ratio expression is obtained, which isolates and detects SI bits from the desired bits. After isolation of these signal points, the POD scheme cancels the residual SI. As compared to the conventional schemes, the proposed POD scheme gives significantly low bit error rate (BER), a clear constellation diagram to obtain the boundary between desired and SI signal points, and increases the receiver's SI cancellation performance in low signal to interference ratio (SIR) environment.     

A 1.9-GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, integrated in a 0.18-mum CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N synthesizer, has a phase noise of -118 dBc/Hz at 600kHz offset and settling time of 15 mus. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA, respectively, from a 3.0 V supply     

Analysis of a homodyne receiver using an injection-lockedsemiconductor laser

The authors study an optical homodyne receiver using an injection-locked semiconductor laser as a local oscillator. The carrier recovery process introduces a phase error, and the calculation of its statistical properties leads to the evaluation of the receiver performance. The analysis shows the dependence of the receiver performance on the injected power and the phase detuning, between the transmitter, and local oscillator electric fields. The receiver performance is affected by the phase noises of the transmitter and local oscillators, by the shot noise of the detectors in the receiver, and by the modulation noise resulting from the injection locking of the local oscillator by a modulated signal     

Link selection based on switching between full‐duplex and half‐duplex modes

Multiple‐input multiple‐output systems can achieve a full sum rate (SR) via full duplex (FD). However, its performance is degraded by self‐interference (SI) that occurs between the transmitter and receiver at the same node and thus is constrained by error floors. Conversely, half duplex (HD) can avoid the SI albeit at lower spectral efficiency, and the slope of its error curve is determined by the diversity order. In this study, a link selection scheme based on switching between FD and HD is examined as a simple method to improve the bit error rate (BER) performance of FD systems. In the proposed link selection algorithm, either FD or HD is selected based on the received minimum distance and signal‐to‐interference plus noise ratio. Simulation results indicate that the proposed hybrid FD/HD switching system offers significant BER performance improvement when compared with that of the conventional FD and FD based on only the received minimum distance under the same fixed SR. Under relatively sufficient SI cancellation, it is demonstrated to outperform the HD with a diversity advantage in low and medium signal‐to‐noise ratio region.