双CMOS成像器同步影像传感系统设计

为了满足双目立体视觉以及多通道视频成像等应用场合对微型化的需求,提出了一种双CMOS成像器同步影像传感系统的设计方法。系统同步获取两个通道的CMOS图像并通过一路视频接口以相同帧率输出影像。系统以CPLD为核心器件,采用乒乓操作实现了对双通道视频数据的存储与传输,并对相应通道的图像以奇数帧和偶数帧的方式输出。CMOS成像器的配置以及数据传输采用模块化的结构设计,使系统的稳定性和灵活性大大提高。实验表明,系统具有良好的显示效果。     

基于CMOS摄像头与FPGA的位置检测系统设计

提出采用CMOS数字摄像头采集并提取黑色胶条位置来控制冷却转鼓速度的方法.系统以FPGA作为核心控制器,采用两片SRAM进行乒乓操作,FPGA根据CMOS摄像头输出的同步信号,将采集到的图像信息存储到一片SRAM中,同时读取另一片SRAM中的图像数据并进行图像处理,黑色胶条位置检测采用简单的灰度阈值二值化方法.给出了部分采集图像及仿真结果.采集图像显示,CMOS摄像头成像质量满足工程要求.仿真结果表明,系统实现了SRAM的乒乓操作,并完成了黑色胶条位置检测.系统与冷却鼓连接,实际运行可靠.     

高速DSP图像处理系统中的乒乓缓存结构研究

高速数字视频处理系统中,为了缓解恒速的视频编解码与变速的DSP图像处理过程之间的矛盾, 常采用乒乓缓存结构作为图像数据输入/输出缓冲器。探讨了乒乓缓存结构的原理及特点,并以高速、大容量的SRAM以及CPLD器件为基础,设计了一种适应于高速DSP图像处理系统的乒乓缓存结构,其特点是速度快、所需器件少,易于与DSP器件接口。     

高速DSP图像处理系统中的乒乓缓存结构研究

高速数字视频处理系统中，为了缓解恒速的视频编解码与变速的DSP图像处理过程之间的矛盾，常采用乒乓缓存结构作为图像数据输入／输出缓冲器。探讨了乒乓缓存结构的原理及特点，并以高速、大容量的SRAM以及CPLD器件为基础，设计了一种适应于高速DSP图像处理系统的乒乓缓存结构，其特点是速度快、所需器件少，易于与DSP器件接口。     

嵌入式LCD控制器对帧缓存操作的关键问题研究

针对嵌入式LCD控制器存在读写帧缓存冲突这一关键性问题,在分析比较两种常见解决方案基础上,提出了一种新的解决方案.设计并实现了一种新的嵌入式LCD控制器.引入时分复用技术解决了读写帧缓存的冲突问题;利用状态转移机制实现了读写SRAM操作.对LCD控制器内部SRAM接口模块的组成结构和工作原理进行了分析,并在Quartu...     

基于以太网技术的立体视觉图像采集系统

设计了基于DSP和以太网技术的立体图像采集平台,将两个CMOS图像传感器获取到的图像对经过DSP处理后通过以太网传输至PC机端接收。采用了乒乓缓存的双RAM结构,扩大了数据吞吐量。就该系统的设计原理及接口连接关系进行了详细论述,最后给出了网络传输流量测试结果。     

MPEG-4隔行方式下P帧运动补偿与逐行方式之比较研究

作为与逐行方式相对应的隔行方式在视频编码中仍有着相当多的应用,通过对隔行方式下xvid开源程序中P帧运动补偿问题的校正,阐述了MPEG-4 P帧运动补偿的一般过程.并对基于帧预测（frame-predicted）的帧间宏块（interMB）运动矢量预测因子的求取进行了介绍,在此基础上,阐明了基于场预测（field-predicted）的帧间宏块上、下半场运动矢量预测因子的计算.给出了帧预测宏块、场预测宏块半象素插值的程序实现,进而对逐行与隔行方式下P帧运动补偿的实现做出较为全面的对比分析.     

数字视频控制芯片的设计

CMOS图像传感器技术逐渐成熟并广泛应用.设计了一款用于CMOS数字摄像头的视频控制芯片,满足30 f/s(帧/s)的视频采集、处理、存储与显示;该芯片集成摄像头寄存器配置块与数据采集接口、外缓存SDRAM接口、外转存储接口以及图像阵列显示接口;设计通过Verilog硬件描述语言进行RTL(Register Transistor Level)建模,在FPGA开发板上进行验证.实验结果证明,该控制芯片可以作为独立专用集成电路,嵌入式应用在数字视频系统中.     

基于CMOS图像传感器的视频采集系统设计

提出了一种采用Altera公司CycloneⅡ系列的FPGA作为主控芯片,采用OV7670这款CMOS图像传感器作为视频信号源并采用sRAM（静态随机存储器）作为数据缓存的实用方案,实现了对图像传感器寄存器配置、图像传感器输出信号采集、图像数据格式转换、图像数据缓存及最终在VGA显示器上进行图像显示的一系列过程。该视频采集系统设计能够很好地满足实时图像的输出需求。     

全彩LED大屏同步显示控制系统的ZBTSRAM控制器设计

在全彩LED大屏同步显示控制系统的设计中,需要采集视频源计算机显卡发送的视频图像信号,并将这些信号传输到远端大屏进行同步显示。由于视频信号速率很大及同步显示的实时性要求,采用ZBT SRAM作为高速视频信号的缓存。利用ZBT SRAM读写操作之间切换快的特点,提出了一种交替读写的存储方法。通过仿真调试表明,此方法极大的节省了存储空间,特别适合用于大屏分辨率大,实时性要求高的场合。     

An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54Gb/s/pin

An 18-Mbit CMOS pipeline-burst cache SRAM achieves a 12.3-Gbyte/s data transfer rate with 1.54-Gbit/s/pin I/O's. The SRAM is fabricated on a 0.18-μm CMOS technology. The 14.3×14.6-mm² SRAM chip uses a 5.59-μm², six-transistor cell. Circuit techniques used for achieving high bandwidth include fully self-timed array architecture, segmented hierarchical sensing with separated global read/write bitlines in different metal layers, a high-speed data-capture technique, a reduced-swing output buffer, and a high-sensitivity, high-bandwidth input buffer     

A 10000 frames/s CMOS digital pixel sensor

A 352×288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-μm CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4×9.4 μm with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 μV/e^-. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm² is only a 7% increase over the conventional 4-Mb DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity     

High speed,low power VLSI CMOS vision sensor for geometric centre object tracking

In this article an object tracking CMOS sensor is presented. The architecture incorporates photo detection devices and pixel level processing elements for capturing and processing the image data and extracting the object's coordinates. The edges of the image scene are extracted by in-pixel edge detectors and the region (object) of interest, selected by the user, is segmented using a switch network. Coordinates of the desired region are obtained by extracting the geometric centre of the region. Tracking of the selected object is then performed by automatic reselection of the region using the updated coordinates. The proposed design presents less sensitivity to threshold adjustments than binarisation techniques. The sensor has been designed as a 64 × 64 pixel VLSI CMOS chip in the 0.35 μm standard CMOS technology. The proposed structure is analysed with regard to its operation in the presence of mismatches and noise. Features of the sensor are reported and compared with some previous object tracking designs. Because the power dissipation is small, the chip is ideal for low-power applications.     

基于ARM9的多路视频采集系统设计

针对近景大视场图像采集,提出了一种基于ARM9芯片S3C2410的多路视频采集系统。使用四个CMOS摄像头（OV7660）进行图像的采集,摄像头输出8位RawRGB格式的图像数据流。系统利用一片FPGA接受摄像头的输出时序,并参考这个时序控制SRAM地址将4个CMOS摄像头的一帧图象数据缓存于4个8位的SRAM中,然后通知ARM读取。ARM以32位总线同时读取图象数据后,将RawRGB格式的图像数据转换成常用的RGB格式,然后显示在LCD上。     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.     

基于FPGA的CMOS传感器高速视频采集系统

依据图像采集和传输的方式和方法的不同,提出了一种以CMOS数字图像传感器作为相机光电转换器件的数据采集方法.设计了一种利用FPGA作为核心控制芯片、USB为传输接口、CMOSOV5620为图像采集芯片的高速视频采集系统.介绍了系统的总体设计结构,给出了各个模块的具体硬件设计方法和软件流程,得出了可行性结论.