嵌入式处理器的软件自测试研究

随着当今科技的发展,集成电路的功能日益强大,制造成本也控制在比较低的水平,与之相对的测试技术的成本却在不断地增加。很显然传统的测试技术已经不能满足当今高速SOC芯片的测试要求,开发新的测试技术已迫在眉睫。本文主要研究基于嵌入式处理器的软件的自测试方法,达到使用低成本的测试机实现高性能的芯片测试的目的。     

互连内建自测试技术的原理与实现

芯片间的互连速率已经达到GHz量级,相比较于低速互连,高速互连的测试遇到了新的挑战.本文探讨了高速互连测试的难点,传统互连测试方法的不足,进而介绍了互连内建自测试(IBIST)的结构以及方法,最后给出IBIST在FPGA中的一种实现.     

嵌入式只读存储器的内建自测试设计

随着存储器件日益向着高速、高集成方向发展,依靠外部设备对嵌入式存储器的测试变得越来越困难,内建自测试是解决这个问题的有效方法;文中详细分析了存储器的故障表现和诊断算法,给出了嵌入式只读存储器的内建自测试的一种设计实现,同时研究了将边界扫描技术与只读存储器的内建自测试相结合、形成层次化系统芯片SoC的设计策略.     

基于DDS的机载嵌入式软件仿真自测试方法北大核心

针对日益复杂的软件测试要求,在保证嵌入式软件的测试效果的同时,应降低测试成本,因此,设计基于DDS的机载嵌入式软件仿真自测试方法。选择S3C44BOX芯片和FPGA-EP2C8作为核心芯片,构建软件仿真测试平台,将测试模型设定为W模型格式,引入LLC聚类系数对测试结果进行分析,完成软件仿真自测试分析过程。由仿真结果可知,其软件异常误检率较低且测试结果精度较高,测试效果得到保证,同时减少测试成本。     

SOC微处理器核测试技术研究

介绍了SOC中微处理器核的几种测试方法(并行测试法,串行测试法,测试接口控制器(TIC)法和内建自测试法)和SOC微处理器核的调试支持,并着重介绍了其中测试接口控制器(TIC)法和内建自测试法两种方法的具体实现。     

可测试性设计技术在一款通用CPU芯片中的应用

可测试性设计(Design-For-Testability,简称DFT)是芯片设计的重要环节,它通过在芯片原始设计中插入各种用于提高芯片可测试性的硬件逻辑,从而使芯片变得容易测试,大幅度节省芯片测试的成本。文中介绍了在一款通用CPU芯片的设计过程中,为提高芯片的易测性而采取的各种可测试性设计技术,主要包括扫描设计(ScanDesign)、存储器内建自测试(Build-in-self-test,简称BIST)以及与IEEE1149.1标准兼容的边界扫描设计(BoundaryScanDesign,简称BSD)等技术。这些技术的使用为该芯片提供了方便可靠的测试方案。     

FPGA芯片的链结构LUT自测试方法研究

基于内建自测试(BIST)思想的FPGA测试方法利用被测芯片中的资源来构建测试所需的TPG或ORA,以减少测试对输入输出引脚和外部ATE的需求。传统的FPGA芯片BIST方法仅考虑自测试结构内被配置为CUT的资源,从而需要进行多次组测试来完成整个芯片的测试。在现有LUT自测试链结构的基础上,通过合理选择TPG的电路结构及测试配置,能够在相同测试开销下增加TPG部分的故障覆盖率,提高测试效率。     

系统芯片IP核间互联总线串扰故障检测模型的BIST实现

文章针对系统芯片IP核间互联总线串扰故障的激励检测问题,在已经提出一种有效的串扰故障渐进式激励检测模型的基础上,给出了一种该渐进式模型的内建自测试(BIST)实现,对其中的测试矢量产生单元、测试响应分析单元以及测试控制单元进行了详细的分析。同时还给出了该BIST结构实现的参数化HDL描述,文章的最后给出了使用综合工具Synopsys对该BIST结构的综合结果。     

ASIC集成电路的可测性设计与技术实现

ASIC集成电路设计开发中的隐含逻辑瑕疵与电路故障是芯片实现的最大困境,针对不同特性的电路提出了内部逻辑扫描、存储器内建自测试、边界扫描链插入以及ATPG自动测试向量生成的解决方案与技术方法,实现了SOC设计开发中逻辑与成片电路的主动侦测与跟踪寻径,经实践证明这些方法大大提高了复杂SOC研制的成功率.     

一种选择多个单元的重新播种内建自测试方法

随着集成电路技术的迅速发展,芯片的集成度越来越高,怎样对电路进行有效测试就显得越来越重要。其中内建自测试被认为是解决测试问题有效方法之一。文中提出了一种选择多个单元的重新播种BIST测试方法,实验结果表明该方法可以降低硬件开销。     

Decreasing Test Qualification Time in AMS and RF Systems

The authors of this article illustrate a means to use design models and simulation testbenches to decrease manufacturing test costs. This technique enables test cost optimization early in the RFIC design phase. In this article, we propose a test set optimization and qualification method that targets test application time, cost, and quality while also decreasing the generation time of production tests. Our approach decreases the manufacturing test cost of AMS and RF SoCs by automatically qualifying and optimizing existing test sets. We present a computer-aided test (CAT) tool, Plasma (platform for system qualification with mixed and analog signals), that uses fault injection and a fault simulation technique to perform test qualification and generation. This tool reduces both test time and test equipment cost using a high-level fault model. Our approach relies on the qualification and optimization of a predefined test set. With this article, we show how to reduce the test optimization time by using behavioral modeling and decreasing the number of simulated circuits. This method reduces the number of simulated fault-free models, thanks to a normal estimation.     

Research and application of cross-test strategy based on component

The technique of Component-Based Development obtained great promotion in recent years. It not only gives profound influence to the technique innovation of software industry, but also brings huge benefit for many other domains. However, the application of fine test methods can simplify test operation, reduce test cost and improve software quality. This paper proposes a kind of cross-test based on component according to traditional software test technique, aiming at the problems produced by new characteristics of software component technique, and verifies a telecommunication system using this test method fmally.     

基于扫描链阻塞技术的时延测试方法

针对时延测试功耗和测试费用较高的问题,提出一种低费用的轮流捕获时延测试方法。采用扫描阻塞技术,将被测电路中的所有扫描单元分成多条子扫描链,使电路中每时刻只有一条子扫描链活跃。在进行故障测试时,通过阻塞一部分子扫描链,使扫描单元得到充分利用。实验结果表明,该方法能降低测试应用时间和测试数据量,且硬件开销较少。     

场景—事件驱动的安全苛求软件系统仿真测试脚本语言研究

脚本技术是实现软件测试自动化技术的有效方法。软件测试脚本化可以降低测试成本,提高测试效率。测试脚本语言是脚本技术的核心,但是目前没有专门针对安全苛求软件测试的脚本语言。因此结合安全苛求软件测试的特点,提出了场景—事件驱动的针对安全苛求软件仿真测试的通用测试脚本语言SED_SCS_STL, 对该语言的设计以及在测试环境中的实现机制进行了阐述,并将其应用于高速铁路CTCS-2级车站列控中心的软件仿真测试中。     

基于虚拟迭代的轿车车身耐久性虚拟试验方法

针对轿车车身开发过程中传统耐久性试验周期长、费用高且不容易在开发前期暴露风险的问题,采用虚拟试验方法,基于实测道路载荷谱并结合多体动力学及有限元仿真技术进行车身疲劳寿命预测.仿真结果与实测应变片台架试验结果一致性很好.该方法能够快速反映风险,大幅缩短开发周期、降低费用.     

中断驱动型嵌入式软件自动测试方案的实现

自动化测试作为一种重要的软件测试技术，如果将其引入嵌入式软件的测试流程，将会对软件的质量、成本和周期带来显著的效果。首先分析了基于模块化设计的嵌入式软件的特点和测试需求，随后提出了一套面向中断驱动型高可靠嵌入式应用的自动化测试解决方案，最后总结了自动化测试的优点及其适用范围。     

An economic dispatch algorithm of combined cycle units

This paper presents a method to solve the economic dispatch (ED) problem for thermal unit systems involving combined cycle (CC) units. The ED problem finds the optimal generation of each unit in order to minimize the total generation cost while satisfying the total demand and generating-capacity constraints. A CC unit presents multiple configurations or states, each state having its own unique cost curve. Therefore, in performing ED, we need to be able to shift between these cost curves. Moreover, the cost curve is not convex for some of these states. Hence, ED becomes a non-convex optimization problem, which is difficult to solve by conventional methods. In this paper we present a new technique, developed to find the global solution, that is based on the calculation of the infimal convolution. The paper includes the results for a case test and we compare our solution with other techniques.     

Conceptual process planning – an improvement approach using QFD,FMEA, and ABC methods

Conceptual process planning (CPP) is an important technique for assessing the manufacturability and estimating the cost of conceptual design in the early product design stage. This paper presents an approach to develop a quality/cost-based conceptual process planning (QCCPP). This approach aims to determine key process resources with estimation of manufacturing cost, taking into account the risk cost associated to the process plan. It can serve as a useful methodology to support the decision making during the initial planning stage of the product development cycle. Quality function deployment (QFD) method is used to select the process alternatives by incorporating a capability function for process elements called a composite process capability index (CCP). The quality characteristics and the process elements in QFD method have been taken as input to complete process failure mode and effects analysis (FMEA) table. To estimate manufacturing cost, the proposed approach deploys activity-based costing (ABC) method. Then, an extended technique of classical FMEA method is employed to estimate the cost of risks associated to the studied process plan, this technique is called cost-based FMEA. For each resource combination, the output data is gathered in a selection table that helps for detailed process planning in order to improve product quality/cost ratio. A case study is presented to illustrate this approach.     

边界扫描技术及其在PCB可测性设计中的应用

阐述了边界扫描技术的基本原理,从设计方法、优化策略及实现技术等方面,对基于边界扫描技术的PCB可测性设计进行了研究,并给出了具体的实现方法;以对某海军导弹通用测试系统中的数据采集电路板进行改进为例,实现了该电路板的可测性设计;经验证,该方法有效地缩短了数据采集电路板的开发周期,降低了其维修测试费用,因而将具有更为广泛的应用前景.     

A robust optimisation framework in composite generation and transmission expansion planning considering inherent uncertainties

Abstract

This paper presents a robust optimisation framework for long-term composite generation and transmission expansion planning problem which considers inherent uncertainties such as load growth, fuel cost and renewable energy output uncertainties. In this paper, a bi-level robust optimisation framework is proposed to accommodate wind output uncertainty in line with the uncertain demanded loads and uncertain fuel cost. The addressed optimisation problem is modelled as a mixed-integer optimisation framework with the objective of providing a robust expansion plan while maintaining the minimum cost expansion. In order to evaluate the robustness of each plan, an off-line Lattice Monte Carlo simulation technique is adopted in this study. The validity of the proposed method is examined on a simple six-bus and modified IEEE 118-bus test system as a large-scale case study. The simulation results show that the presented method is both satisfactory and consistent with expectation.