3.3 V 11 bit delta-sigma modulator using first-generation SIcircuits

The authors present the design of a second-order switched-current delta-sigma modulator having optimum signal swing and its implementation using first-generation switched-current circuits with an improved clock feedthrough compensation scheme. Measurement results distinguish the modulator from other designs in that the modulator has a small chip area, and has low voltage and power requirements, while achieving an 11 bit dynamic range     

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.      

Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link

As the technology scales down, shrinking geometry and layout dimension, on- chip interconnects are exposed to different noise sources such as crosstalk coupling, supply voltage fluctuation and temperature variation that cause random and burst errors. These errors affect the reliability of the on-chip interconnects. Hence, error correction codes integrated with noise reduction techniques are incorporated to make the on-chip interconnects robust against errors. The proposed error correction code uses triplication error correction scheme as crosstalk avoidance code (CAC) and a parity bit is added to it to enhance the error correction capability. The proposed error correction code corrects all the error patterns of one bit error, two bit errors. The proposed code also corrects 7 out of 10 possible three bit error patterns and detects burst errors of three. Hybrid Automatic Repeat Request (HARQ) system is employed when burst errors of three occurs. The performance of the proposed codec is evaluated for residual flit error rate, codec area, power, delay, average flit latency and link energy consumption. The proposed codec achieves four magnitude order of low residual flit error rate and link energy minimization of over 53 % compared to other existing error correction schemes. Besides the low residual flit error rate, and link energy minimization, the proposed codec also achieves up to 4.2 % less area and up to 6 % less codec power consumption compared to other error correction codes. The less codec area, codec power consumption, low link energy and low residual flit error rate make the proposed code appropriate for on chip interconnection link.     

A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS

A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.     

An AlGaAs/InGaAs pseudomorphic HEMT modulator driver IC with lowpower dissipation for 10-Gb/s optical transmission systems

An optical modulator driver integrated circuit (IC) has been developed for 10-Gb/s optical communication systems. To achieve both high-frequency (HF) operation and low power dissipation, 0.2-μm T-shaped gate AlGaAs/InGaAs pseudomorphic high electron-mobility transistors (HEMTs) have been employed for their large transconductance g_m of 610 mS/mm and high cutoff frequency f_T of 67.5 GHz. In addition, optimizing input logic swing, switching transistor size in the output driver, and using cascode-current mirror circuits with small output conductance enable power dissipation as low as 1 W to be achieved at a 10-Gb/s nonreturn-to-zero (NRZ) signal output with 3 V_p._p. This is the lowest value ever reported for power dissipation. As an additional function, the output-voltage swing can be controlled in the range from 2 to 3.3 V_p._p. by the current mirror circuit for the purpose of adjusting the optical-output-signal duty factor through an optical modulator     

2.5Gb/s 16:1MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for optical fiber communication based on TSMC 0.25 μm CMOS technology is presented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8 mm2.     

标准数字工艺下16位精度低压低功耗ΣΔ模数调制器设计

针对输入信号频率在20 Hz～24 kHz范围的音频应用,该文采用标准数字工艺设计了一个1.2 V电源电压16位精度的低压低功耗ΣΔ模数调制器。在6 MHz采样频率下,该调制器信噪比为102.2 dB,整个电路功耗为2.46 mW。该调制器采用一种伪两级交互控制的双输入运算放大器构成各级积分器,在低电源电压情况下实现高摆率高增益要求的同时不会产生更多功耗。另外,采用高线性度、全互补MOS耗尽电容作为采样、积分电容使得整个电路可以采用标准数字工艺实现,从而提高电路的工艺兼容性、降低电路成本。与近期报道的低压低功耗ΣΔ模数调制器相比,该设计具有更高的品质因子FOM。     

A 14 mW 2.5 MS/s 14 bit Σ∆ Modulator Using Split-Path Pseudo-Differential Amplifiers

This paper presents the design and experimental results of a 1.25 MHz signal bandwidth 14 bit CMOS SigmaDelta modulator. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. A prototype chip has been designed and fabricated in a 0.25 mum CMOS technology with a core area of 0.27 mm². Experimental results show that an 84 dB dynamic range is achieved over a 1.25 MHz signal bandwidth when clocked at 125 MHz. The power dissipation is 14 mW at 2.4 V including on-chip voltage reference buffers.     

A low-power SRAM using hierarchical bit line and local sense amplifiers

This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to V/sub DD//10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K/spl times/32 bits is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.     

0.18μm CMOS 10Gb/s光接收机限幅放大器

利用TSMC 0.18μm CMOS工艺设计了应用于SDH系统STM-64(10 Gb/s)速率级光接收机中的限幅放大器.该放大器采用了改进的Cherry-Hooper结构以获得高的增益带宽积,从而保证限幅放大器在10Gb/s以及更高的速率上工作.测试结果表明,此限幅放大器在10Gb/s速率上,输入动态范围为42dB(3.2mV~500mV),50Ω负载上的输出限幅在250mV,小信号输入时的最高工作速率为12Gb/s.限幅放大器采用1.8 V电源供电,功耗110mW.芯片的面积为0.7mm×0.9mm.     

A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic rangeusing the switched-opamp technique

The design and implementation of a very low supply voltage/low power ΔΣ modulator is presented. It is based on the switched-opamp technique, which allows low voltage operation with a standard process and without voltage multiplication. The design methodology is illustrated with a second-order single-loop ΔΣ modulator. The chip is implemented in a 0.7-μm CMOS process with standard threshold voltages. The power supply is 1.5 V and the power dissipation is only 100 μW. The measured dynamic range in the speech bandwidth of 300-3400 Hz is 12 b. The total harmonic distortion (THD) is lower than -72 dB     

80-Gb/s Low-Driving-Voltage InP DQPSK Modulator With an n-p-i-n Structure

We present a traveling-wave-electrode InP-based differential quadrature phase-shift keying modulator with a novel n-p-i-n waveguide structure. The structure features low electrical and optical propagation losses, which allow the modulator to operate at a high bit rate together with a low driving voltage and a low insertion loss. We successfully demonstrate 80-Gb/s modulation with a driving voltage of only 3 $hbox{V}_{rm pp}$ in a push–pull configuration. The chip size is just 7.5 mm$, times ,$ 1.3 mm.      

用于SDH STM-64光发射机的GaAs PHEMT激光驱动器

介绍了用于SDH系统STM-64速率光发射机用的激光二极管/光调制器驱动器集成电路的设计。电路采用法国OMMIC公司的0.2μm GaAs PHEMTs工艺设计并制造,可以驱动激光二极管和电吸收式调制器。电路由输入匹配电路、预放大电路、源极跟随器、主放大电路、电容耦合电流放大器和输出电路组成。电路芯片面积1.0mm×0.9mm。测试结果表明,电路采用单一正5V电源供电,直流功耗1.4W,可以在10Gb/s速率下正常工作,眼图良好。最高工作速率高于20Gb/s,输出电压幅度2.8V。     

Low-power and high-performance techniques in global interconnect signaling

In this article, two accurate and efficient approaches are proposed to optimize the power and delay of global interconnects in VLSI ICs. We modify the conventional buffer insertion and low swing methods for delay and power optimization of various lengths of the global interconnects. As such, we address non-equidistance buffer insertion (NEBI) and current-mode driver and receiver (CMDR) techniques along with our smart optimization procedure. It is shown that the optimized low swing CMDR technique is efficient for global interconnects of the length equal or longer than 5 mm, and the improved buffer insertion technique, NEBI, is a perfect choice for the short global interconnects. Additionally, a random search algorithm known as simulated annealing (SA), improved by an intelligent method using a piecewise linear and exponential cost function, is employed for optimization of the power and delay. To this end, we have implemented a smart CAD tool that works interactively with HSPICE to achieve accurate and reliable design results. For verification purposes, several circuits are designed and simulated in 0.25, 0.18, and 0.13 μm CMOS technologies. The simulation results verify a significant reduction in the power and delay of global interconnects compared to other methods in the literature.     

A 10-Gb/s optical transmitter module with a monolithicallyintegrated electroabsorption modulator with a DFB laser

A compact 10-Gb/s optical transmitter module with small-chirp output was developed by using a monolithically integrated electroabsorption modulator with a distributed-feedback laser. This module can be operated at a bit rate of more than 10 Gb/s at 1.55 μm, and shows a high modulated output power of ~1 dBm with a low optical coupling loss of 3.2 dB between chip and fiber. A multifunctional and compact optical isolator with a monitor photodiode was also developed to decrease noise     

Low-power CMOS digital design with dual embedded adaptive powersupplies

A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in the decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design     

Uncooled performance of 10-Gb/s laser modules with InGaAlAs-InP and InGaAsP-InP MQW electroabsorption Modulators integrated with semiconductor amplifiers

Uncooled operation of long-reach high performance C-band 10 Gb/s of optical modulator modules is presented. Modules consisting of a distributed feedback laser and a chip with a monolithically integrated electroabsorption modulator and semiconductor optical amplifier based on multiquantum-well structures of both InGaAsP-InP and InGaAlAs-InP material systems are presented. Dispersion penalty of 1 dB over 94-km transmission, output power above 0 dBm, and low extinction ratio variation are demonstrated over an 80/spl deg/C temperature range. A simple analysis of the quantum confined Stark effect is employed to explain the temperature-dc bias voltage dependence.     

全双工逆向调制回复空间光通信系统性能评价

基于逆向调制反射器(MRR)的空间光通信系统因其结构紧凑、可免去链路一端的捕跟(APT)系统、功耗低等优点,是空间光通信系统研究热点之一。提出采用双波长激光发射实现全双工逆向调制回复空间光通信结构,并基于该结构对强度调制解调模式,通信距离为300 km,通信速率为1 GHz下的地面站对近地小卫星全双工通信链路进行了链路计算及通信误码率的分析。当MRR端口径为0.1 m时,通信链路余量大于5 dB,通信误码率优于10-15,满足通信链路的要求。并进一步分析了仿真结果存在的缺陷。结果表明所提出的空间光通信结构在小卫星对地面站全双工激光通信是可行的,是未来空间光通信系统发展趋势之一。     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

On the design considerations of solid-state power amplifiers for satellite communications: A systems perspective

Conventional solid-state power amplifier (SSPA) design approach isolates radio frequency (RF) design from communication theory. In this paper, a unified SSPA design approach is proposed, which optimizes SSPA parameters (bias voltage and input RF signal power) to minimize total DC power consumption while satisfying received SNR constraint specified by the link budget. The effect of SSPA nonlinearity is quantified by the error vector magnitude measured at its output and the corresponding received SNR degradation is analyzed. Using the quantitative metrics for received SNR, it is possible to evaluate highly nonlinear SSPA classes such as Class-B or deep-Class AB, which are normally not considered in conventional SSPA design approach to be used in satellite communication applications.