Emission probability of hot electrons for highly doped silicon-on-sapphire IGFET

Experimental measurements of the probability of emission of hot electrons into the oxide of silicon-on-sapphire (SOS) MOS devices are presented for high doping levels. The experimental method is derived from the optically induced hot electron experiment as proposed by Ning. The dependence of the emission probability on device parameters and applied voltage is analyzed emphasizing the lucky electron model and the sensitivity of the model to device characterization. We found that the expressionP = P'_{0} exp (-d/lambda_{eff})describes the experimental data very well, takingP'_{0} = 0.5andlambda_{eff} = 95Å. It shows that hot carrier properties of SOS are the same as those of bulk silicon. The results also show that hot electron related instabilities can arise for bias voltages lower than 2 V when the doping level reaches 1 × 10¹⁸At/cm³.     

Laser annealing of GaAs implanted with low doses of selenium ions

GaAs samples were implanted with 100–400 keV, 10¹²–10¹⁴/cm²Se⁺ ions and annealed using undiffused and diffused pulsed ruby-laser beams with the samples held at various temperatures.

The resulting surface and structural defects as observed by various microscopic and spectroscopic methods are related to measured electrical properties of implanted GaAs, and the causes of the observed poor and lack of electrical activation of samples identified.

Laser irradiation of samples (T ≈ 516°C) induces surface damage in the form of regular parallel broken lines with a periodicity of about 0.69 μm, the wavelength of the ruby laser.

A diffused laser beam (0.5 J/cm²) reduces surface vaporisation and eliminates periodic surface structures. The measured electrical properties are still poor.     

LASOS—laser annealed silicon on sapphire

Laser annealing techniques were successfully incorporated into standard MOS/SOS processing to increase transistor channel mobility and processing yield. Silicon islands were photolithographically defined and chemically etched (by KOH) on standard SOS wafers. The islands were exposed to radiation from an excimer laser (λ = 2490 Å) having a pulse duration of 25 ns, a beam size in the range of 0.1-0.2 cm², and an energy density in the range of 0.5 - 1.0 J/cm². Using standard processing techniques MOS transistors were fabricated and characterized. It was found that exposure at an energy density of ∼0.80 J/cm²results in rounding the Si island edges, thus eliminating the "V"-shaped groove profile of the gate oxide and improving Al step coverage. The electrical characteristics of MOS transistors fabricated over laser annealed islands exhibited a 30-percent increase in channel mobility with a small negative shift (<0.2 V) in the transistor threshold voltage.     

SiGe pMODFETs on silicon-on-sapphire substrates with 116 GHzfmax

The dc and microwave results of Si_0.2Ge_0.8/Si_0.7Ge_0.3 pMODFETs grown on silicon-on-sapphire (SOS) substrates by ultrahigh vacuum chemical vapor deposition are reported. Devices with L_g=0.1 μm displayed high transconductance (377 mS/mm), low output conductance (25 mS/mm), and high gate-to-drain breakdown voltage (4 V). The dc current-voltage (I-V) characteristics were also nearly identical to those of control devices grown on bulk Si substrates. Microwave characterization of 0.1×50 μm² devices yielded unity current gain (f_T) and unilateral power gain (f _max) cutoff frequencies as high as 50 GHz and 116 GHz, respectively. Noise parameter characterization of 0.1×90 μm² devices revealed minimum noise figure (F_min) of 0.6 dB at 3 GHz and 2.5 dB at 20 GHz     

Device fabrication in {100} silicon-on-oxide produced by a scanning CW-laser-induced lateral seeding technique

By using a CW-laser-beam-induced lateral seeding technique, which is a zone-melting crystal-growth process, single-crystal silicon-on-oxide with{100}orientation has been obtained. To adopt this process for silicon-on-insulator (SOI) MOS transistor fabrication, a masking level has been added to an exisiting n-MOSFET mask set so that a fully recessed oxide layer may be grown in selected regions of a silicon wafer; the exposed silicon region becomes the seed region. After depositing a 0.5-µm-thick layer of undoped low-pressure CVD polysilicon on the wafer, a laser process is performed to induce epitaxial growth in the polysilicon-on-silicon region, which in turn seeds the zone growth of the polysilicon-on-oxide region as the beam is traversed across the surface of the wafer. N-channel MOS transistors have been fabricated in the silicon-on-oxide material using projection printing lithography. Both complete-island-etch (CIE) and LOCOS techniques have been used for device-to-device and device-to-substrate isolation. Surface electron mobilities as high as 740 cm²/V . s, comparable to that obtainable in bulk-type devices, have been measured in 5-µm channel-length devices. It is shown that the back interface between the recrystallized silicon and the oxide layer is the dominant contributor to the subthreshold leakage current due to a combined effect of a high fixed oxide charge density and drain-induced barrier lowering. A high dose (sim 10^{12}cm^-2) deep boron implantation centered at the back interface and a back-gate bias have been shown to be effective in suppressing the leakage current to as low as 1-pA/µm channel width at VDS= 2 V, comparable to the best results obtained in silicon-on-sapphire (SOS).     

A compact fiber-optic magnetometer employing an amorphous metalwire transducer

A compact fiber-optic magnetometer constructed using a short piece of amorphous metal wire (5-cm long×100-μm diameter) as the magnetostrictive transducer is discussed. The inherently large ratio of length to cross-sectional area results in a low demagnetization along the axial direction. A magnetostrictive constant of 5×10^-5 /Oe², which is 10-50 times larger than the reported values for transducers made from Metglas ribbons, was measured. Minimum detectable magnetic fields on the order of 10^-5 Oe/Hz^1/2 at 1 Hz were achieved using a 5-cm-long sensing fiber     

Fabrication of SOS MOSFETs using two-step doping with excimer laser

Using two-step doping with excimer laser, p-channel MOSFETs were fabricated in thin silicon films on sapphire (SOS). Source and drain p ⁺ layers were formed using two-step doping with only one melting pulse of excimer laser. Devices were processed at room temperature except for the LPCVD gate oxide deposition at 450°C. High-quality thin film transistors (TFTs) were fabricated with on/off current ratio of 7 and a field effect hole mobility of 145 cm²/V s     

Experimental determination of electron drift velocity in 4H-SiC p+-n-n+ avalanche diodes

4H-SiC p⁺-n-n⁺ diodes of low series resistivity (<1×10^-4 Ω·cm²) were fabricated and packaged. The diodes exhibited homogeneous avalanche breakdown at voltages U_b=250-270 V according to the doping level of the n layer. The temperature coefficient of the breakdown voltage was measured to be 2.6×10^-4 k^-1 in the temperature range 300 to 573 K. These diodes were capable of dissipating a pulsed power density of 3.7 MW/cm² under avalanche current conditions. The transient thermal resistance of the diode was measured to be 0.6 K/W for a 100-ns pulse width, An experimental determination of the electron saturated drift velocity along the c-axis in 4H-SIC was performed for the first time, It was estimated to be 0.8×10⁷ cm/s at room temperature and 0.75×10⁷ cm/s at approximately 360 K     

Ion-sensitive field-effect transistors with inorganic gate oxide for pH sensing

Ion-sensitive field-effect transistors (ISFET's) have been fabricated by using silicon films on sapphire substrates (SOS). Using this structure SiO2, ZrO2, and Ta2O5films are examined as hydrogenion-sensitive materials, and Ta2O5film has been found to have the highest pH sensitivity (56 mV/pH) among them. The measured pH sensitivity of this SOS-ISFET's is compared with the theoretical sensitivity based on the site-binding model of proton dissociation reaction on the metal oxide film and good agreement between them is obtained.     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

Normal-incidence, high-temperature, mid-infrared, InAs-GaAsvertical quantum-dot infrared photodetector

The growth, fabrication, and characterization of a normal-incidence, high-temperature, mid-wavelength infrared, InAs-GaAs vertical quantum-dot infrared photodetector with a single Al_0.3 Ga_0.7As current-blocking barrier are described and discussed in detail. A specific detectivity ≈3×10⁹ cmHz^1/2/W is measured for a detector temperature of 100 K at a bias of 0.2 V. Detector characteristics are measured for temperatures as high as 150 K. The superior low bias performance of the vertical quantum-dot infrared photodetector ensures its compatibility with commercially available silicon read-out circuits necessary for the fabrication of a focal plane array     

Reactively sputtered tantalum pentoxide thin films for integrated capacitors

The aim of this work was to develop a deposition process for a high-dielectric constant tantalum pentoxide for integrated capacitors. Thin films were deposited reactively on glass wafers using a radio-frequency magnetron sputtering cluster tool at various O₂/Ar flow ratios. By using 2 MeV ⁴He⁺ backscattering spectroscopy and X-ray diffraction, the films obtained showed a stoichiometric orthorhombic β-Ta₂O₅ phase at 20% O₂ in the sputtering gas flow. With low-frequency measurements (f=100 kHz), a 200×200-μm² square metal–insulator–metal (MIM) capacitor with copper electrodes and a 340-nm thick dielectric gave a capacitance density of 0.066 μF/cm², with a quality factor (Q) of 650. The value of the relative permittivity (_r) was approximately 25 determined from MIM capacitors of various sizes. The surface roughness of the 376-nm thick oxide film was found to be small: 0.255 nm. The largest measured capacitor (200×200 μm²) gave reasonable results at low frequencies. When the frequency was increased (100 kHz–20 GHz) only for the smaller capacitors (30×30 μm²) the capacitance remained constant. However, the Q values decreased of the smaller capacitors as a function of frequency. Processed tantalum pentoxide MIM capacitors possessed reasonable electrical properties below 2 GHz and good potential for further improvement.     

GaAs/AlGaAs heterojunction Pnp bipolar transistors grownon (100) Si by molecular beam epitaxy

GaAs/AlGaAs Pnp heterojunction bipolar transistors (HBTs) were fabricated and tested on (100) Si substrates for the first time. A common-emitter current gain of β=8 was measured for the typical devices with an emitter area of 50×50 μm² at a collector current density of 1×10⁴ A/cm² with no output negative differential resistance up to 280 mA, highest current used. A very high base-collector breakdown voltage of 10 V was obtained. Comparing the similar structures grown on GaAs substrates, the measured characteristics clearly demonstrate that device grade hole injection can be obtained in GaAs on Si epitaxial layers despite the presence of dislocations     

Multichip module photovoltaic miniarrays

In this work a novel concept of photovoltaic mini array assembly is described based on a flip-chip multichip module technology. A number of arrays composed of 15 series-connected 2 mm² c-Si photovoltaic cells have been fabricated, achieving a packaging density of 40 cells/cm². Measurements of the dark I-V characteristic confirmed that the resistive losses of the approach are small and do not degrade the electrical characteristics of the array. Nearly 0.5 mW/cm ² delivered density power, and 7 V in open circuit conditions were typically measured under normalized solar spectrum (AM1.5 100 mW/cm ²), and around 6.3 mW/cm² and 8.5 V using a 150 W commercial lamp placed at 5 cm distance from the panel     

Thin-film transistors incorporating a thin, high-quality PECVD SiO2 gate dielectric

Thin-film transistors (TFTs) have been made that incorporate a thin (~380 Å), high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO₂ film as the gate dielectric in a staggered-inverted structure. Threshold voltages and mobilities have been found to be in the range of 1.6-2.4 V and 0.20-0.25 cm² V^-1 s^-1, respectively, where the exact values are dependent on the measurement technique used. Very low gate leakage currents (<10^-11 A) were recorded when measured using a ramped I-V technique, even for electric fields as high as 5×10⁶ V/cm     

4H-SiC MOSFETs utilizing the H2 surface cleaningtechnique

The H₂ cleaning technique was examined as the precleaning of the gate oxidation for 4H-SiC MOSFETs. The device had a channel width and length of 150 and 100 μm, fabricated on the p-type epitaxial layer of 3×10¹⁶ cm^-3. The gate oxidation was performed after the conventional RCA cleaning, and H₂ annealing at 1000°C. The obtained channel mobility depends on the pre-cleaning process strongly, and was achieved 20 cm²/N s in the H₂ annealed sample. The effective interface-state density was also measured by the MOS capacitors fabricated on the same chips, resulting 1.8×10¹² cm^-2 from the photo-induced C-V method     

Lamp phosphors and color gamut in positive-column gas-discharge cells for TV displays

Phosphors suitable for a full-color TV display in recently reported new high-luminance (360-fL green) high-efficiency (3.4-lm/W) gas-discharge cells have been determined: blue Sr5Cl(PO4)3Eu⁺², green Zn2SiO4:Mn⁺², and red Y2O3Eu⁺³. A decrease in color gamut with increasing current density has been measured and related to gas-discharge effects rather than phosphor saturation, using experimental results and a simplified model calculation. Aging of the green phosphor was measured and its causes are discussed.     

Double-injection phenomena under magnetic field in SOS films: A new generation of magnetosensitive microdevices

We analyze several sensors belonging to the magnetodiodes family and realized with silicon on sapphire (SOS) technology. They are: p⁺-n-n⁺, Schottky and filamentary magnetodiodes. These very simple devices have "micronic" dimensions compatible with VLSI and exhibit sensitivities which are two orders of magnitude higher than conventional sensors: 30 V/T have been measured on Schottky magnetodiodes without amplification and for low power dissipation. It is shown that the optimum operating as well as the improvement of the device design require conditions of high level injection, corresponding to double-injection phenomena: thus the establishment and the behavior of the so-called "semiconductor regime" have been systematically studied for numerous diodes with different geometries and dopings. Narrowest structures, shorter than 20 µm and with the doping below 10²²m^-3are shown to be suitable. The detailed analysis of different magnetosensitivities is completed with experiments on noise, temperature, and high magnetic field.     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

New self-aligned T-gate InGaP/GaAs field-effect transistors grownby LP-MOCVD

This paper reports on self-aligned T-gate InGaP/GaAs FETs using n ⁺/N⁺/δ(P⁺)/n structures. N⁺ -InGaP/δ(P⁺)-InGaP/n-GaAs forms a planar-doped barrier. The inherent ohmic gate of camel-gate FETs together with a highly selective etch between an InGaP and a GaAs layers offers a self-aligned T-shape gate with a reduced effective length. A fabricated device with a reduced gate dimension of 1.5×100 (0.6×100) μm² obtained from 2×100 (1×100) μm² gate metal exhibits an extrinsic transconductance, unity-current gain frequency, and unity-power gain frequency of 78 (80) mS/mm, 9 (19.5), and 28 (30) GHz, respectively