基于FPGA的Turbo译码器设计

Turbo码良好的纠错性能为众多研究者所公认,其相关理论和实现技术一直是该领域的研究热点。本文主要围绕如何用FPGA实现Turbo码译码器,介绍了Turbo码迭代译码的硬件实现算法以及流水线译码概念,并利用Altera的Flex10k10芯片实现了该译码器。性能测试实验表明,该基于FPGA实现的译码器最高速率可达到8Mbps,性能相比于理论译码器性能下降控制在0.5dB以内,具有广阔的应用前景。     

基于MAX-Log-MAP算法和DSP芯片的Turbo译码器

Turbo码又称为并行级联卷积码,其重要的特性就是实现了伪随机编码的思想,但要实现译码低误码率却要以降低整个编译码系统的效率和增加延时为代价。因此,本文通过分析Turbo码迭代译码原理和MAX-Log-MAP算法,根据性能要求和可行性考虑,以DSP芯片ADSP-TS101和MAX-Log-MAP译码算法来实现Turbo译码器的设计,实验结果表明,该系统误码率较低、延时性能符合要求,工作稳定。     

基于软件无线电的Turbo码编码通信系统实现

为保障和提高无线信道下的数据传输可靠性和灵活性,基于通用软件无线电外设（USRP）平台设计和实现了以Turbo码作为信道编码方案的通信系统.系统发射机可采用1/2或1/3码率的Turbo码对传输数据进行编码,接收机通过软解调方法和软输入软输出的Max-Log-MAP迭代译码算法获得编码增益.仿真与测试结果表明,采用Turbo码作为编码方案可有效对抗噪声和衰落,降低传输误比特率,进而提高无线通信系统的可靠性.此外,通过文件传输等应用,进一步验证了本系统的可行性.     

基于FPGA的卷积码的编/译码器设计

卷积码作为通信系统中重要的编码方式,以其良好的编码性能,合理的译码方法,被广泛应用。本文在介绍卷积码原理的基础上,详细阐述了基于FPGA的卷积码的编/译码器的设计。值得一提的是,卷积码的译码采用维特比译码算法,利用了状态路径度量计算、保存路径转移过程和回溯译码等方法,在硬件实现上能有效地减少存储量、降低功耗,提高整个编/译码器的性能。最后进行了模拟仿真,结果显示编译码的效果比较理想,达到了设计的目的。     

Turbo译码器滑动窗的改进及其FPGA设计

针对Turbo译码算法的硬件实现进行了研究,在综合分析目前Turbo译码器硬件实现优缺点的基础上,提出了一种基于FPGA的滑动窗硬件实现算法新结构,对存储、时延、硬件消耗等细节做了一系列优化,并在Xilinx的XC3S1500 FPGA上实现。仿真结果表明,该算法结构在降低时延、保证码性能的基础上减少了硬件消耗。     

CDMA2000中的Turbo码的改进

本文提出了第3代移动通信系统CDMA2000标准中采用的Turbo码编码和译码的改进算法。通过Matlab仿真对卷积码和改进后的Turbo码在CDMA2000前向信道中的性能比较分析,证明改进后的Turbo码性能优异并能够通过减少迭代次数从而减轻译码复杂度。     

Inmarsat移动卫星通信系统中Turbo码的应用

在分析Turbo码结构和原理的基础上，介绍了Inmarsat-M4和Inmmarsat-F系统中实现“压缩频带的高速数据(HsD)传输”的核心技术。着重阐述Turbo码多电平调制结合方式、信道状态信息提取、译码算法和实现上有待解决的关键问题。     

基于Turbo码的卫星通信系统仿真研究

介绍了一种基于Turbo码的仿真方法。对Turbo码在卫星通信系统中的应用进行了较为详细的仿真建模和性能分析,设计了Turbo码的编码和译码器部分,并对仿真过程中的关键问题加以分析,通过仿真结果与理论比较,验证了仿真的正确性。     

电力线通信中LDPC译码器的优化设计与实现

电力线信道的噪声干扰很强,严重影响通信系统性能。文章提出了一种适于电力线通信中LDPC码的译码器硬件结构优化方法,并通过FPGA设计实现。算法的修正过程只包含简单的算术和逻辑运算,便于FPGA实现。本文方案提供的结构与常用的部分并行译码结构相比,节省了大量硬件资源。经软硬件仿真验证,硬件BP实现结构性能接近浮点BP算法,能应用于电力线通信等信噪比较低的传输领域。     

分组乘积Turbo码动态迭代译码算法分析与优化

分组乘积Turbo码 (简称TPC码)是一类将分组码进行串行级联,并采用分组交织器构成的级联码,是一种构造十分简单的纠错码,它是香农信息理论提出后第一个在非零码率时可以实现无误码传输的纠错编码.采用迭代译码方法,可发挥该码的良好性能,并特别适合于高速硬件译码.良好的纠错性能使得TPC码正在被广泛的应用.本文首先对TPC码的编码结构和译码算法进行介绍,其后对TPC码的动态迭代译码进行分析与仿真,最后对其算法提出了优化方法.     

一种改善LDPC译码性能的新方法

由于LDPC码可以逼近香农限,近年来在国内外编码研究与应用中受到广泛关注,然而,LDPC码迭代译码存在误码平底,限制了LDPC码的进一步应用.陷阱集是导致LDPC码误码平底的主要因素,为了消除陷阱集的影响,提出一种基于陷阱集变量节点消息重置译码方法.当译码器进入陷阱状态后,重新计算陷阱集变量点消息,使译码器在后续迭代过...     

面积优先的CCSDS Turbo码编译码器的设计与实现

本文设计出符合CCSDS标准的Turbo编译码器,包含伪随机序列模块与帧同步模块.在实现编码器时针对标准要求,对伪随机化处理及其恢复和帧同步检测提出了解决方案;而在相应的译码器设计中,本文权衡硬件实现复杂度与处理时延等因素,优先考虑面积因素提高元件的重复利用率和降低复杂度,并阐述了其实现过程.最后基于Verilog HDL设计出RTL级14位固点数据的Turbo编译码器以及仿真验证平台,与用MATLAB语言设计的相同指标的浮点数据译码器进行性能比较,得到设计验证.     

Adaptation of turbo coding and equalization in turbo equalization for time-varying and frequency-selective channels

A number of authors have sought to combine equalization and decoding in an iterative system in order to reduce the effects of frequency and temporal dispersiveness of time-varying frequency-selective channels. In the recent literature, several architectures based on these iterative systems have been proposed. One can note architectures which combine a maximum a posteriori (MAP) equalizer and decoder, architectures formed by an interference canceller and MAP decoder, architectures implementing a decision feedback equalizer and a MAP decoder, etc. Most of these architectures require accurate channel estimation to adapt the equalizer filters or to execute the MAP equalizers. This article presents a turbo equalizer architecture for time-varying frequency-selective channels without channel estimators. The proposed turbo equalizer consists of an interference canceller in direct-adaptation mode and a turbo decoder. In order to reduce noise correlation, the addition of a transverse filter to the interference-canceller architecture is proposed. The reliability factor for variable time-varying frequency-selective channels is also redefined in order to improve the performance of the turbo decoder. The architecture of the proposed turbo equalizer reduces considerably the effects of frequency and temporal dispersiveness of time-varying frequency-selective channels depending on the normalized Doppler frequency range.     

FPGA实现旋转变压器R2D变换方法的研究

旋转变压器到数字信号转换的过程称之为R2D变换,也可称之为解码。实现R2D有专用的解码芯片,但实际使用中发现解码芯片很难通过电磁兼容实验,尝试采用软件的方式来实现。软件实现关键是对反三角函数的求解,经典方法是采用CORDIC算法实现,CORDIC在求解超越函数有一定的优越性,流水线结构更是可以满足高速运算,因此应用较为广泛。但解码方法是多样的,还同时介绍了一种角度跟随实现解码的方法,该方法通过构建反馈模型实现角度的逐渐逼近,最终实现解码。这两种方法都很容易在FPGA内实现,仿真分析表明它们的精度都能够满足需求,适合于大多数应用场合。     

一种多元LDPC-CPM优化方法及性能仿真分析

为了解决二元低密度奇偶校验(LDPC)码与高阶连续相位调制(CPM)级联的系统在卫星通信、深空通信方面传输性能不足的问题，提出了一种多元LDPC-CPM优化方法。首先采用多元LDPC码与高阶CPM串行级联形成多元LDPC-CPM系统获取更好的传输误码性能。其次考虑到多元LDPC码的传统译码算法复杂度过高，难以硬件实现的问题，设计了一种改进型的Mixed-Log-FFT-BP算法，通过去除加法与查表运算中对数似然比的求解，降低译码复杂度。最后针对多元LDPC-CPM系统涉及参数过多问题，提出一种性能逐步收敛的参数优化方法。仿真结果表明，与优化前的系统相比，优化后的系统在中高信噪比下，误码性能有1～1.2 dB的提升，且系统复杂度较低。     

A novel decoding scheme based on recalculation for double binary convolutional turbo code

To decrease the storage complexity of a double binary convolutional turbo code (DB‐CTC) decoder, a novel decoding scheme is proposed in this paper. Different from the conventional decoding scheme, only a part of the state metrics is stored in the last‐in first‐out (LIFO) state metrics cache (SMC). Based on an improved maximum a posteriori probability (MAP) algorithm, we present a method to recalculate the unstored state metrics at the corresponding decoding time slot, and discuss in detail the procedures of the recalculation are discussed. Because of the compare–select–recalculate processing operations, compared to the classical decoding scheme, the proposed decoding scheme reduces the storage complexity of SMC and the amount of memory accesses by approximately 40% while limiting involved computational cost. Moreover, simulation results show that the proposed scheme achieves good decoding performance, which is close to that of the well‐known Log‐MAP algorithm. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Iterative channel estimation and decoding of turbo-coded OFDM symbols in selective Rayleigh channel

This work deals with the detection of turbo-coded symbols in orthogonal frequency-division multiplexed (OFDM) systems. OFDM symbol detection requires channel estimation, which is often carried out using known pilots. In this paper, an iterative detector composed of a turbo decoder and a channel estimator is proposed. These modules perform jointly and exchange soft information through an iterative process. The decoder consists of the maximum a posteriori Bahl-Cocke-Jelinek-Raviv (MAP-BCJR) algorithm, and the channel estimator is based on the minimum mean-square error (MMSE) criterion. The proposed approach allows for the use of all available information, increases the quality of channel estimation, and improves the system performance. This paper also proposes a new expression of the channel reliability factor used by the MAP-BCJR decoding algorithm. This metric depends on signal-to-noise ratio and the channel estimation error variance. The effect of the channel reliability factor and of the channel estimation error are investigated.