一种计算微波电路的并行算法——FDTD—Diakoptics

ＦＤＴＤ－Ｄｉａｋｏｐｔｉｃｓ将复杂的微波电路分割为若干简单的子电路,使用有限时域差分方法（ＦＤＴＤ）独立求解每个子电路的时域特性,使用并行算法连接各子电路,最终得到整个电路的特性。本方法适用于结构复杂,规模较大的微波电路的分析设计,与整个电路使用ＦＤＴＤ进行设计研究的方法比较,本算法在保证相同数值精度的条件下可以提高计算效率五倍左右,故具有广泛的应用前景。     

一种时间序列预测方法在二维时域有限差分法中的应用

本文将一种时间序列预测方法与二维时域有限差分（ＦＤＴＤ）法相结合,并应用均匀微波平面传输线的特性参数计算,该混合方法特别适用于尺寸很细微的ＭＭＩＣ传输线,而且可以精确地计算非理想导体的损耗。与传统的ＦＤＴＤ法相比,大大节约了计算时间,提高了效率。计算结果与测量非常一致。     

微波电路的时域设计方法

本文研究了几种微波电路和无件和ＦＩＲ数字滤波器的直接结构形式的内在关系。从而将ＦＩＲ数字滤波器的窗函数设计技术引用到微波电路的设计中，提出了这些微波电路的时域设计方法。该方法具有简捷，有闭合形式公式可循等优点，尤其适合于工程设计。     

N阶色散媒质的FDTD法与数学信号处理技术

提出了一种新的Ｎ阶色散媒质的时域分析方法,并将其表征为一组无限冲击响应滤波器,将色散媒质在ＦＤＴＤ中的表述问题转化为数字滤波器（ＩＩＲ）的设计问题。改进ＦＤＴＤ能分析处理与频率有关的电磁场问题。为验证此方法的有效性和可靠性,用此方法计算了高斯平面波脉冲入射Ｎ阶色散媒质的情况,计算结果与解析值非常吻合。     

单模光纤偏振模色散的测试

偏振模色散在近年来成为光纤光缆的一个重要特性参数。本文着眼于ＰＭＤ测试的原理和方法，首先指出注重ＰＭＤ的统计特性是进行ＰＭＤ测试的一个重要原则；绾而按频域和时域对测试ＰＭＤ的方法进行分类，并分析了目前常用的几种ＰＭＤ测试方法，例如ＪＭＥ，ＷＳＥＣ，ＰＳＰ，ＩＦ，ＷＳＦＦＴ和ＰＯＴＤＲ法，讨论了它们各自的优缺点。最后对这些测试方法进行了有益的比较。     

FDTD法计算高频单极天线特性

用时域有限差分法（Ｆｉｎｉｔｅ Ｄｉｆｆｅｒｅｎｃｅ Ｔｉｍｅ Ｄｏｍａｉｎ Ｍｅｔｈｏｄ）计算天线阻抗特性,可以使用不同的激励方式,文章比较了采用不同激励方式时,天线的输入阻抗。文中的主要内容是将表面阻抗法用于ＦＤＴＤ中,计算架设在介质平面上单极天线的辐射特性,并用ＦＤＴＤ法计算了介质平面上铺设不同尺寸的导体平面时,单极天线的输入阻抗随导体平面尺寸变化的特性。     

Thompson—FDTD方法中的两步法

本文将流体力学领域的微分－－Ｔｈｏｍｐｓｏｎ变换与时域有限差分（ＦＤＴＤ）技术结合起来，所形成的Ｔｈｏｍｐｓｏｎ－ＦＤＴＤ方法，首次用来计算和分析任意形状介质体的电磁散射特性，该方法至少具有两个明显的优点，可以把不规则形体变换成规则形体，有利于精确匹配边界条件；可以任意调配网格分布，有利于提高计算精度，其数值实现进一步证实了该方法能精确模拟任意形状介质目标的电磁散射过程。     

一种提取多导体互连线等效电路频变分布参数的时域全波方法

本文给出了一种基于时域有限差分（ＦＤＴＤ）法，提取多导体互连线等效电路频变分布参数的时域全波方法．提取出的频率分布参数可用来研究含有多种导体互连线的高速集成电路（ＶＬＳＩ）系统的时域响应．由于在全波分析中电压和电流没有唯一的定义，本文还给出了基于不同电压、电流定义而得到的电路参数之间的转换关系．计算结果表明：这种方法是可靠的．     

一个基于并行时域Diakoptics的离散格林函数的新算法

本文介绍一个计算系统离散格林函数的新方法－－并行时域Ｄｉａｋｏｐｔｉｃｓ法,将一个较简单的子域,用有时域差分法计算各子域的时域响应,用并行射ｉａｋｏｐｔｉｃｓ计算任意彼此相邻的两个子域间的电磁耦合,并最终得到整个系统的离散格林函数,与传统的模式匹配法和有限时域差分法（ＦＤＴＤ）比较,本方法可处理几何结构更为复杂的问题,并且具有较好的精度及计算效率。     

时域有限差分法计算微带电路中圆柱介质谐振器的谐振频率

采用时域有限差分法（ＦＤＴＤ）计算了微带电路中圆柱介质谐振器的谐振频率,求解了孤立ＤＲ、介质衬垫ＤＲ以及屏蔽的ＤＲ。计算结果与变分法计算的结果一致,验证了时域有限差分法的有效性,使时域有限差分法接近实际工程设计需要。     

分裂法与FET技术相结合的电路动态分析

提出了分裂法与FFT技术相结合的动态电路分析法。把复杂动态电路分割成若干个线性子电路和一组联络支路(线性和非线性)。在任意长时间间隔内,用多端动态电源等效替代线性子电路。在互联电路的计算中,应用了FFT技术,该方法可降低分析复杂电路的难度,提高计算效率。     

开关电容积分器的瞬态行为模型

对电路进行行为级模拟的关键是建立电子子模块的行为模型，用以描述电路模块的功能以及电路非理想效应的影响。本文采用瞬态分析方法，建立了基本模拟单元电路开关电容积分 的行为模型。由于对积分器中的运算放大器采用了单极点跨导运放模型，考虑了其有限增益、带宽、转换速率和输出阻抗的影响，提高了开关电容积分器行为模型的精度。电路模拟的结果表明，模型的误差在３％以内。     

A process-insensitive thermal protection circuit

A novel process-insensitive thermal protection structure has been developed.This circuit contains several sub-circuits such as band-gap reference,reference output buffer,resistance voltage divider branch,and hysteresis circuit.By using reference buffer,the precise reference voltage from band-gap reference is delivered to resistance voltage divider branch and is divided precisely.Then the threshold temperatures of this protection circuit can be set by this precise voltage,unaffected by process variation and mismatch.A hysteresis circuit is also used here to prevent thermal oscillation.This circuit is fabricated in TSMC 0.18μm CMOS technology,and occupies about 3×10~4μm~2 chip area.     

Hybrid asynchronous circuit generation amenable to conventional EDA flow

This work proposes a new method of synthesizing asynchronous circuits targeting its practical usability. The key contribution of this work is finding an effective technique of inter-mixing the two design principles namely handshaking based single-rail and timing annotated (i.e., quasi-delay insensitive (QDI)) dual-rail of asynchronous circuits. Precisely, we propose a clever way of partitioning an input (synchronous) circuit to transform it into a circuit with single-rail and dual-rail sub-circuits and of designing seamless interface to stitch the sub-circuits. Our proposed synthesis flow closely links to industrial design automation tools with standard cell libraries to enhance the practicality and productivity. Experimental results show that the designs produced by our approach expose partial or full combinations of high-performance, low-power consumption, great immunity to delay and noise variability, and mitigation to the side-channel attacks in hardware security.     

Static frequency divider featuring reduced circuit complexity byutilizing resonant tunneling diodes in combination with HEMTs

A static frequency divider constructed with resonant tunneling diodes (RTDs) in combination with HEMTs is proposed and demonstrated. The circuit complexity is reduced drastically. The proposed circuit is fabricated using InP-based RTD/HEMT monolithic integration technology. Proper operation is demonstrated at room temperature by a quasi-static test pattern. The circuit includes two sub-circuits which behave like D-latches. Each sub-circuit consists of only three components. This number of components is one fifth of that required to construct a D-latch using conventional SCFL technology. The strong nonlinear I-V characteristics of RTD's are fully utilized for this reduction     

Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.     

An efficient heuristic force directed placement algorithm based on partitioning

An efficient heuristic force directed placement algorithm based on partitioning is proposed for very large-scale circuits. Our heuristic force directed approach provides a more efficient cell location adjustment scheme for iterative placement optimization than the force directed relaxation (FDR) method. We apply hierarchical partitioning based on a new parallel clustering technique to decompose circuit into several level sub-circuits. During the partitioning phase, a similar technique to ‘terminal propagation’ was introduced so as to maintain the external connections that affect cell adjustment in sub-circuit. In these lowest level sub-circuits, the heuristic force directed algorithm is used to perform iterative placement optimization. Then each pair of sub-circuits resulted from bisection combine into a larger one, in which cells are located as the best placement state of either sub-circuits. The bottom-up combination is done successively until back to the original circuit, and at each combination level the heuristic force directed placement algorithm is used to further improve the placement quality. A set of MCNC (Microelectronics Centre of North-Carolina) standard cell benchmarks is experimented and results show that our placement algorithm produces on average of 12% lower total wire length than that of Feng Shui with a little longer CPU time.     

单片视频D／A转换器SDA1016的电路分析与设计

对单片视频Ｄ／Ａ转换器ＳＤＡ１０１６进行了电路原理分析和优化设计，该结果可作为电路研制及应用的参考。给出了ＳＤＡ１０１６视频ＤＡＣ的复合视频应用电路。采用了某些模拟技术，实现了ＳＤＡ１０１６全直流分析、子电路（块）的瞬态分析，是ＳＰＩＣＥ用于ＬＳＩ电路分析和优化设计的成功例证。     

基于ESOP最大加权输出相容类的可逆电路综合方法

充分挖掘乘积项在多个函数输出之间的共享因素来降低可逆电路的量子成本是基于积之异或和（Exclusive-Sums-Of-Products,ESOP）的可逆电路综合方法要解决的一个重要问题.提出一种基于最大加权输出相容类的可逆电路综合方法.该方法先借助零抑制多输出决策图对立方体集合进行输出等价类划分,并采用贪心策略计算最大加权输出相容类,然后对最大加权输出相容类进行综合,以使混合极性多控制Toffoli门以及可逆子电路在尽可能多的输出变量线之间共享.通过立方体聚类挖掘等价类中立方体间的结构相似性,并对文字数较多的立方体实施分解,进一步降低可逆电路的量子成本.使用RevLib多输出函数对所提出方法进行了验证,结果表明所提出方法可以很好地挖掘乘积项在多个函数输出之间的共享因素,能够降低由ESOP综合所得可逆电路的量子成本,并且具有较高的时间效率.     

Efficient Realization of Parity Prediction Functions in FPGAs

In this paper, we propose an AND/XOR-based technology mapping method for efficient realization of parity prediction functions in field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve an excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as parity prediction functions, efficiently. We conduct experiments using the parity prediction functions with respect to MCNC benchmark circuits. With the proposed approach, the number of configurable logic blocks (CLBs) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), respectively. The total equivalent gate counts are reduced by 65.5%, maximum combinational path delay is reduced by 56.7%, and maximum net delay is reduced by 80.5% compared to conventional methods.