Scalable hybrid computation with spikes

We outline a hybrid analog-digital scheme for computing with three important features that enable it to scale to systems of large complexity: First, like digital computation, which uses several one-bit precise logical units to collectively compute a precise answer to a computation, the hybrid scheme uses several moderate-precision analog units to collectively compute a precise answer to a computation. Second, frequent discrete signal restoration of the analog information prevents analog noise and offset from degrading the computation. And, third, a state machine enables complex computations to be created using a sequence of elementary computations. A natural choice for implementing this hybrid scheme is one based on spikes because spike-count codes are digital, while spike-time codes are analog. We illustrate how spikes afford easy ways to implement all three components of scalable hybrid computation. First, as an important example of distributed analog computation, we show how spikes can create a distributed modular representation of an analog number by implementing digital carry interactions between spiking analog neurons. Second, we show how signal restoration may be performed by recursive spike-count quantization of spike-time codes. And, third, we use spikes from an analog dynamical system to trigger state transitions in a digital dynamical system, which reconfigures the analog dynamical system using a binary control vector; such feedback interactions between analog and digital dynamical systems create a hybrid state machine (HSM). The HSM extends and expands the concept of a digital finite-state-machine to the hybrid domain. We present experimental data from a two-neuron HSM on a chip that implements error-correcting analog-to-digital conversion with the concurrent use of spike-time and spike-count codes. We also present experimental data from silicon circuits that implement HSM-based pattern recognition using spike-time synchrony. We outline how HSMs may be used to perform learning, vector quantization, spike pattern recognition and generation, and how they may be reconfigured.     

Analysing the Robustness of Surfing Circuits

Surfing is a technique for implementing high-speed digital pipelines that exploits the analog dynamics of the underlying circuits. Thus, verification must consider the analog behaviour of the design. We have presented a method for analysing the robustness of surfing circuits. We formulate noise margin analysis as a non-linear optimization problem where we find the smallest disturbance waveform that results in a qualitative change in the behavior of the circuit. We present a practical method for solving these optimization problems based on deriving a sensitivity matrix for the small-signal response of the circuit.     

基于Simulink的数模混合电路仿真平台设计与实现

针对数模混合电路仿真精度与性能之间的矛盾问题和仿真工业级复杂数模混合电路时仿真工具存在主流芯片和电路模块不足问题,提出了一种粘合模式的数模混合仿真平台模型架构,基于该架构设计并实现了一种基于Simulink软件,通过嵌入数字电路和模拟电路主流仿真引擎获得充足主流芯片和电路模块支持的数模混合电路仿真平台,设计了一种结合了拓扑排序算法的仿真控制方式,实现了对工业级复杂电路进行流程化、模块化的数模混合仿真;最后通过一个能够时序上可以逻辑拆分的典型数模混合电路仿真验证了仿真平台的有效性。     

Multichannel signal processors for multielement IR FPA

Structure and circuit solutions for implementing adaptive multichannel analog and digital signal preprocessing circuits integrated with readout circuits are considered. Experimental results of investigating multichannel signal preprocessing readout circuits and IR FPA based on them are represented. The article is published in the original.     

Pulse-stream VLSI neural networks mixing analog and digitaltechniques

The pulse-stream technique, which represents neural states as sequences of pulses, is reviewed. Several general issues are raised, and generic methods appraised, for pulsed encoding, arithmetic, and intercommunication schemes. Two contrasting synapse designs are presented and compared. The first is based on a fully analog computational form in which the only digital component is the signaling mechanism itself-asynchronous, pulse-rate encoded digital voltage pulses. In this circuit, multiplication occurs in the voltage/current domain. The second design uses more conventional digital memory for weight storage, with synapse circuits based on pulse stretching. Integrated circuits implementing up to 15000 analog, fully programmable synaptic connections are described. A demonstrator project is described in which a small robot localization network is implemented using asynchronous, analog, pulse-stream devices.     

采用计数器存储权值的人工神经网络的实现

文中提出了一种采用计数器存储权值的人工神经网络的实现方案。数字权值采用计数器存储,突触电路和神经元电路用模拟电路来实现。数字权值经脉冲宽度调制电路转换为脉冲信号作为模拟突触电路的输入信号。因而权值可以长期存储,对权值的修改易于实现,突触神经元电路结构简单,融合了人工神经网络模拟实现和数字实现的优点。对于智能计算机的实现具有重要的意义。     

Stochastic neural networks

The first purpose of this paper is to present a class of algorithms for finding the global minimum of a continuous-variable function defined on a hypercube. These algorithms, based on both diffusion processes and simulated annealing, are implementable as analog integrated circuits. Such circuits can be viewed as generalizations of neural networks of the Hopfield type, and are called “diffusion machines.” Our second objective is to show that “learning” in these networks can be achieved by a set of three interconnected diffusion machines: one that learns, one to model the desired behavior, and one to compute the weight changes.     

An Investigation of Scalable SIMD I/O Techniques with Application to Parallel JPEG Compression

The problem inherent with any digital image or digital video system is the large amount of bandwidth required for transmission or storage. This has driven the research area of image compression to develop more complex algorithms that compress images to lower data rates with better fidelity. One approach that can be used to increase the execution speed of these complex algorithms is through the use of parallel processing. In this paper, we address the parallel implementation of the JPEG still-image compression standard on the MasPar MP-1, a massively parallel SIMD computer. We develop two novel byte alignment algorithms which are used to efficiently input and output compressed data from the parallel system, and present results which show real-time performance is possible. We also discuss several applications, such as motion JPEG, that can be used in multimedia systems.     

Equivalence between some dynamical systems for optimization

It is shown by the derivation of solution methods for an elementary optimization problem that the stochastic relaxation in image analysis, the Potts neural networks for combinatorial optimization and interior point methods for nonlinear programming have common formulation of their dynamics. This unification of these algorithms leads us to possibility for real time solution of these problems with common analog electronic circuits.     

Time Constrained Verification of Analog Circuits using Model-Checking Algorithms

In this contribution we present algorithms for model checking of analog circuits enabling the specification of time constraints. Furthermore, a methodology for defining time-based specifications is introduced. An already known method for model checking of integrated analog circuits has been extended to take into account time constraints. The method will be presented using three industrial circuits. The results of model checking will be compared to verification by simulation.     

Vision-Based Robotic Motion Control for Non-autonomous Environment

A visual servo control system with SOPC structure is implemented on a retrofitted Mitsubishi Movemaster RV-M2 robotic system. The hardware circuit has the functions of quadrature encoder decoding, limit switch detecting, pulse width modulation (PWM) generating and CMOS image signal capturing. The software embedded in Nios II micro processor has the functions of using UART to communicate with PC, robotic inverse kinematics calculation, robotic motion control schemes, digital image processing and gobang game AI algorithms. The digital hardware circuits are designed by using Verilog language, and programs in Nios II micro processor are coded with C language. An Altera Statrix II EP2S60F672C5Es FPGA chip is adopted as the main CPU of the development board. A CMOS color image sensor with 356 ×292 pixels resolution is selected to catch the environment time-varying change for robotic vision-based servo control. The system performance is evaluated by experimental tests. A gobang game is planned to reveal the visual servo robotic motion control objective in non-autonomous environment. Here, a model-free intelligent self-organizing fuzzy control strategy is employed to design the robotic joint controller. A vision based trajectory planning algorithm is designed to calculate the desired angular positions or trajectory on-line of each robotic joint. The experimental results show that this visual servo control robot has reliable control actions.     

A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity

We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.     

现代模拟电路故障诊断技术发展综述

模拟电路的故障率长期以来居高不下,但模拟电路由于其客观世界信号本质无法完全被数字电路取代,模拟电路的可靠性也成为制约电路系统可靠性的关键因素。主要针对模拟电路的软故障诊断方法进行了研究,分析了模拟电路在故障诊断中的难点,分别对传统和智能化的故障诊断发展和研究现状进行了综述,展望了未来模拟电路故障诊断的发展趋势。     

The feasibility of motion and structure from noisy time-varying image velocity information

This research addresses the problem of noise sensitivity inherent in motion and structure algorithms. The motion and structure paradigm is a two-step process. First, we measure image velocities and, perhaps, their spatial and temporal derivatives, are obtained from time-varying image intensity data and second, we use these data to compute the motion of a moving monocular observer in a stationary environment under perspective projection, relative to a single 3-D planar surface. The first contribution of this article is an algorithm that uses time-varying image velocity information to compute the observer's translation and rotation and the normalized surface gradient of the 3-D planar surface. The use of time-varying image velocity information is an important tool in obtaining a more robust motion and structure calculation. The second contribution of this article is an extensive error analysis of the motion and structure problem. Any motion and structure algorithm that uses image velocity information as its input should exhibit error sensitivity behavior compatible with the results reported here. We perform an average and worst case error analysis for four types of image velocity information: full and normal image velocities and full and normal sets of image velocity and its derivatives. (These derivatives are simply the coefficients of a truncated Taylor series expansion about some point in space and time.) The main issues we address here are: just how sensitive is a motion and structure computation in the presence of noisy input, or alternately, how accurate must our image velocity information be, how much and what type of input data is needed, and under what circumstances is motion and structure feasible? That is, when can we be sure that a motion and structure computation will produce usable results? We base our answers on a numerical error analysis we conduct for a large number of motions.     

Artificial neural networks based dynamic priority arbitration for asynchronous flow control

Accesses to physical links in Networks-on-Chip need to be appropriately arbitrated to avoid collisions. In the case of asynchronous routers, this arbitration between various clients, carrying messages with different service levels, is managed by dedicated circuits called arbiters. The latter are accustomed to allocate the shared resource to each client in a round-robin fashion; however, they may be tuned to favor certain messages more frequently by means of various digital design techniques. In this work, we make use of artificial neural networks to propose a mechanism to dynamically compute priority for each message by defining a few constraints. Based on these constraints, we first build a mathematical model for the objective function, and propose two algorithms for vector selection and resource allocation to train the artificial neural networks. We carry out a detailed comparison between seven different learning algorithms, and observe their effectiveness in terms of prediction efficiency for the application of dynamic priority arbitration. The decision is based on input parameters: available tokens, service levels, and an active request from each client. The performance of the learning algorithms has been analyzed in terms of mean squared error, true acceptance rate, number of epochs and execution time, so as to ensure mutual exclusion.

     

Determination of camera parameters for character motions using motion area

We propose a method to determine camera parameters for character motion, which considers the motion by itself. The basic idea is to approximately compute the area swept by the motion of the character’s links that are orthogonally projected onto the image plane, which we call “motion area”. Using the motion area, we can determine good fixed camera parameters and camera paths for a given character motion in the off-line or real-time camera control. In our experimental results, we demonstrate that our camera path generation algorithms can compute a smooth moving camera path while the camera effectively displays the dynamic features of character motion. Our methods can be easily used in combination with the method for generating occlusion-free camera paths. We expect that our methods can also be utilized by the general camera planning method as one of heuristics for measuring the visual quality of the scenes that include dynamically moving characters.     

DNA computing approach for automated test pattern generation for digital circuits

Testing of digital circuits is a compute intensive problem. This article deals with the problem of automated test pattern generation for large digital circuits. A new evolutionary approach based on DNA computing is presented, which exploits the computational power of DNA molecules to solve the problem. A Boolean formula in conjunctive normal form is extracted from the circuit under test and then the proposed algorithm based on DNA computing is used to find the solution satisfying that formula. Exploiting the massive parallelism and recombination properties of DNA molecules, a test vector is found in polynomial time i.e., O (nk). Its effectiveness in terms of Fault coverage, CPU time and Test vector generated is compared with some existing classical approaches like simulated annealing and genetic algorithms.     

数字图像处理算法评估系统的硬件设计

为了能对不同的数字图像处理算法进行评估,采用了USB2．0总线技术传送数字图象数据到数字图像处理系统,在硬件设计上采用DSP＋FPGA来完成图像处理任务。整个系统具有处理能力强,重现性好,能完成各种图像处理算法评估。     

一种改进的视频分割网络及其全局信息优化方法EI北大核心CSCD

提出了一种基于注意力机制的视频分割网络及其全局信息优化训练方法.该方法包含一个改进的视频分割网络,在对视频中的物体进行分割后,利用初步分割的结果作为先验信息对网络优化,再次分割得到最终结果.该分割网络是一种双流卷积网络,以视频图像和光流图像作为输入,分别提取图像的表观信息和运动信息,最终融合得到分割掩膜(Segmentation mask).网络中嵌入了一个新的卷积注意力模块,应用于卷积网络的高层次特征与相邻低层次特征之间,使得高层语义特征可以定位低层特征中的重要区域,提高网络的收敛速度和分割准确度.在初步分割之后,本方法提出利用初步结果作为监督信息对表观网络的权值进行微调,使其辨识前景物体的特征,进一步提高双流网络的分割效果.在公开数据集DAVIS上的实验结果表明,该方法可准确地分割出视频中时空显著的物体,效果优于同类双流分割方法.对注意力模块的对比分析实验表明,该注意力模块可以极大地提高分割网络的效果,较本方法的基准方法(Baseline)有很大的提高.     

A flexible mixed-signal image processing pipeline using 3D chip stacks

This work presents a highly flexible mixed-signal CMOS image sensor suitable for smart camera applications. These systems need to fit different constraints regarding power consumption, speed and quality, and the optimal compromise may differ depending on the application. Moreover, the best implementation of a desired image processing task may be in the analog or the digital domain, or even a combined computation. Different aspects starting from the image sensor and signal acquisition up to the pre-processing in analog and digital domain are investigated in this paper to optimize not just one part of the system, but the whole system altogether. Moreover, it is shown that analog processing algorithms can improve signal quality, processing speed and latency while being able to save power, which is important for real-time systems. In order to be able to carry out spatial operations, the state-of-the-art sensor is modified to be able to read out multiple pixels at the same time. This allows analog spatial filter operations which consume significantly less power. As an example, an averaging filter is described which needs less than 5.3 % of the power–time product of a digital implementation for one computation. To enhance data throughput and flexibility, 3D chip stacking is proposed to partition the sensor in smaller units and enable massively parallel processing.