基于通用信号处理平台的数字声呐仿真研究

传统的声呐设计,采用专用硬件配以专用软件实现实时信号处理,开发周期长,可靠性可维修性较低。利用通用信号处理平台实现数字声呐设计是今后的一种发展方向。分析了数字声呐设计的基本原则,研究了一种利用通用信号处理平台实现传统数字声呐的仿真设计方法。分析了通用信号处理平台的总体设计、硬软件组成及功能特点,利用该平台,按照50%冗余设计,完成了48路圆柱型基阵主动声呐的实时仿真设计。通过该仿真设计实例,说明数字声呐可以方便地采用通用信号处理平台来实现。     

Architectures and visual-processing applications of multimedia DSPs

Programmable digital signal processors (DSPs) are playing an increasingly important role in visual-processing applications such as three-dimensional graphics, image processing, and digital video. DSP architecture improvements, tuned to the data flow and algorithmic requirements of visual processing, are driving the proliferation of DSP use in these application areas. DSP software architectures are also undergoing significant changes to address the new challenges and opportunities created by the use of DSPs in these applications. This article provides an overview of the architecture and software developments in DSPs to meet the demanding needs of visual-processing applications. © 1998 John Wiley & Sons, Inc. Int J Imaging Syst Technol 9: 416–422, 1998     

耐电压测试仪自动检测系统的研究和应用

该文介绍了耐电压测试仪的工作原理以及自动检测系统的软硬件设计。其中耐电压测试仪校验仪以16位微处理器为核心,14位ADC进行模数转换,DSP数字信号处理器读取数字量进行计算和处理,最后通过显示电路显示测量结果。具有较强的抗电磁干扰性、高准确性和稳定性及长期工作的可靠性。软件系统采用方便快捷的C++Builder语言编写,从而实现集过程自动检测、数据自动处理与报告自动生成于一体的自动检定系统。系统运行效果良好。     

FPAA-based MHO distance relay considering CVT transient supervision

Present-day numerical relays provide remarkable capabilities such as monitoring, recording and communication. These capabilities are considered as secondary priority whereas speed and reliability are the two most important characteristics of a protective relay. Even though present-day numerical relays have provided considerable capabilities and advantages, they have not improved speed of operation in comparison to their solid-state counterparts. The idea of applying mixed signals processing using advanced analogue and digital technology in several applications has started. Use of advanced programmable analogue technology, which is known as field programmable analogue arrays (FPAAs), seems to have the potential to be used in protective relays. Hybrid hardware using both digital signal processor (DSP) and FPAAs is proposed to implement mho distance relay considering capacitor voltage transformer (CVT) transient supervision for low and high system impedance ratio (SIR) systems. Test results are reported and compared with a commercial relay test results.     

通用型高频宽带ADCP信号处理系统设计与实现

文章介绍了一种高频采集、数字解调滤波的通用型高频宽带声学多普勒流速剖面仪(Acoustic Doppler Current Profilers,ADCP)信号处理系统的设计和实现过程。该系统以现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)+数字信号处理器(Digital Signal Processor,DSP)+低功耗单片机(Mixed Signal Processor 430,MSP430)为架构平台,利用三者在信号处理领域的不同优势,采用软硬件协同设计的方式,解决了高频ADCP高采样率、高数据处理能力及低功耗的应用需求,在保证数据处理速度的基础上实现了相位的严格正交,且通过参数化配置实现了多频段、多功能的通用性设计,可适用于不同频段的走航式及自容式ADCP中。经湖上试验验证,该系统测速精度高,性能稳定可靠,达到了预期的设计指标。该系统的软硬件划分方式对其他高频海洋设备的研制具有一定的参考价值。     

红外焦平面失效元处理方法及软硬件实现

失效元对红外焦平面阵列器件成像质量的影响较大。本文在给出失效元定义的基础上,对失效元的产生机理进行了分析,并给出了具体的失效元检测方法。基于DSP实现了红外图像的硬件处理系统并编写了失效元处理的软件程序,实现了失效元的自动检测和校正。实验结果表明,所设计的软硬件符合实时性、可靠性的要求,取得了较好的处理效果。     

被动定向浮标数字解复用技术

介绍了被动定向浮标信号传输系统中复合信号解复用的工作原理,推导了解复用的过程,解释了罗盘补偿矢量传感器自转对浮标测向的影响。提出了一种解复用的数字信号处理算法．在信号处理板上软件实现解复用。设计了一种软件导频锁相环,解决了偶极子信号解调过程中频率相位精确跟踪的问题。该技术降低了浮标接收机的复杂性,保证了通道一致性,提高了可靠性和定向精度,同时降低了浮标的成本。通过仿真对导频锁相环的性能作了评价,并通过湖上试验对其进行了验证。     

A digital-signal-processor-based measurement system for on-linefault detection

This paper deals with the design, construction, and setting up of a measurement apparatus, based on an architecture using two parallel digital signal processors (DSP's), for on-line fault detection in electric and electronic devices. In the proposed architecture, the first DSP monitors a device output on-line in order to detect faults, whereas the second DSP estimates and updates the system-model parameters in real-time in order to track their eventual drifts. The problems which arose when the proposed apparatus was applied to a single-phase inverter are discussed, and some of the experimental results obtained in fault and nonfault conditions are reported     

A power quality monitoring system: a case study in DSP-basedsolutions for power electronics

Programmable digital signal processors (DSPs) are emerging as the processors of choice in monitoring and control of high-end power electronics systems. This paper adopts a case study approach to illustrate a development methodology for DSP-based solutions. The unique features of DSP chips that make them ideal for real-time applications are highlighted. Power electronics systems where DSPs have been used are indicated. A case study in which a DSP-based solution was developed for a power quality monitoring application is presented. Through the case study, the issues involved in adopting a system architecture, selecting a DSP, and developing software for an application are discussed. The methodology described in this paper presents broad guidelines which can be intelligently applied to develop DSP-based solutions to meet specific requirements     

基于可重构数据路径的DSP的研究与实现

研究了一种基于可重构数据路径的信号处理器结构。其具有功耗低,速度快,灵活性较高等特点,可以做为个人信息处理SoC的核心处理器。而且,该结构具有粗粒度和结构级可重构的优点,适合有规律、高重复性和计算量大的任务,如多媒体信号处理和专门计算等。本文首先分析了实现该结构的关键技术,然后提出了实现方案和验证方法。     

基于DSP的无线电引信起爆控制技术研究

在分析数字信号处理器特点的基础上,阐述了基于DSP的引信起爆控制系统的总体方案,研究了DSP应用于引信起爆控制的硬件结构和软件实现方法.数字信号处理技术对目标信号进行实时检测与分析,有效提高了目标信息的处理速度和控制准确度,提高了引信抗干扰能力和适时起爆的可靠性,为引信数字化改造提供技术支持.     

Software reliability allocation of digital relay for transmission line protection using a combined system hierarchy and fault tree approach

Digital relay is a special purpose signal processing unit in which the samples of physical parameters such as current, voltage and other quantities are taken. With the proliferation of computer technology in terms of computational ability as well as reliability, computers are being used for such digital signal processing purposes. As far as computer hardware is concerned, it has been growing steadily in terms of power and reliability. Since power plant technology is now globally switching over to such computer-based relaying, software reliability naturally emerges as an area of prime importance. Recently, some computer-based digital relay algorithms have been proposed based on frequency-domain analysis using wavelet-neuro-fuzzy techniques for transmission line faults. A software reliability allocation scheme is devised for the performance evaluation of a multi-functional, multi-user digital relay that does detection, classification and location of transmission line faults.     

A digital signal-processing instrument for impedance measurement

A digital signal processing (DSP)-based instrument for impedance measurement is proposed. It implements two measurement techniques: the first technique allows the tracking of a time varying impedance to be carried out, and the second assures that good accuracy is obtained in reasonable measurement times. Both the software and the hardware of a prototype model are described in detail. The measurement rates and accuracy are evaluated and compared with those obtained using a reference Digibridge for a wide range of impedance values     

生物芯片扫描分析系统DSP软件设计

生物芯片扫描分析系统是生物芯片能否得到广泛应用的关键仪器。针对传统生物芯片扫描分析系统结构复杂、处理速度慢、体积庞大等弱点,引入DSP处理器完成扫描控制和全自动数据分析处理。DSP/BIOS的运用使得系统DSP软件设计简单化。概述了整个系统的结构,详细介绍了生物芯片扫描分析系统DSP软件结构和设计,包括DSP/BIOS的运用模块、BOOT的过程、扫描控制模块、数据处理模块和HPI模块。目前该系统已进入了稳定工作的状态。     

数字设备界面系统中的交互安全研究

目的 根据数字产品的交互特点和交互安全的要求，建立一个数字产品安全交互的框架，从而为相关产品设计人员提供新的设计视角。方法 通过对数字产品的使用习惯进行分析，总结和提出数字产品界面交互安全的设计细节要求，从而制定出符合安全交互的设计模型。结论 数字设备交互安全的核心是用户，其安全交互涉及界面构架、图标、色彩、反馈、硬件适配多个方面，数字设备的交互过程对用户生理和心理均会产生影响。对于交互安全，应当在产品设计之初进行统筹考虑，以用户为本设计硬件与软件界面，从而将界面设计作为产品竞争力的来源。     

包装机械中电机控制DSP器件与串行EEPROM的通讯

介绍了一种在包装机械中电机控制DSP芯片ADMC401与串行EEPROM之间的硬件和软件接口技术.并在ADMC401处理器板上实现了ADMC401的串行口与串行EEPROM之间的通讯.     

基于VPX标准的RapidIO交换和Flash存储模块设计

针对某阵列信号处理系统中的互连总线和数据存储问题,提出了基于VPX标准的RapidIO交换和Flash存储模块的设计方案,并完成了该模块的软硬件设计.介绍了新一代高速串行总线RapidIO和VPX标准,根据VPX标准设计板卡,利用Tsi578交换机设计RapidIO网络实现多DSP系统的并行处理结构.研究了RapidI...     

Development of a multitechnology field-programmable gate array suitable for photonic information processing

The architecture of a novel, multitechnology field-programmable gate array (FPGA) is introduced. Based on conventional complementary metal-oxide semiconductor VLSI technology this architecture has demonstrated the feasibility of reconfigurable and programmable hardware for prototyping photonic information processing systems. We report that this new FPGA architecture will enable the design of reconfigurable systems that incorporated technologies outside the traditional electronic domain. The smart photoreceivers monolithically integrated in the new FPGA architecture can receive optically encoded signals in parallel and process them with user programmable logic hardware.     

An embryonic approach to reliable digital instrumentation based on evolvable hardware

Embryonics encompasses the capability of self-repair and self-replication in systems. This paper presents a technique based on reconfigurable hardware coupled with a novel backpropagation algorithm for reconfiguration, together referred to as evolvable hardware (EHW), for ensuring reliability in digital instrumentation. The backpropagation evolution is much faster than genetic learning techniques. It uses the dynamic restructuring capabilities of EHW to detect faults in digital systems and reconfigures the hardware to repair or adapt to the error in real-time. An example application is presented of a robust BCD to a seven-segment decoder driving a digital display. The results obtained are quite interesting and promise quick and low cost embryonic schemes for reliability in digital instrumentation.     

Enhanced Portable LUT Multiplier with Gated Power Optimization for Biomedical Therapeutic Devices

Digital design of a digital signal processor involves accurate and high-speed mathematical computation units. DSP units are one of the most power consuming and memory occupying devices. Multipliers are the common building blocks in most of the DSP units which demands low power and area constraints in the field of portable biomedical devices. This research works attempts multiple power reduction technique to limit the power dissipation of the proposed LUT multiplier unit. A lookup table-based multiplier has the advantage of almost constant area requirement’s irrespective to the increase in bit size of multiplier. Clock gating is usually used to reduce the unnecessary switching activities in idle circlet components. A clock tree structure is employed to enhance the SRAM based lookup table memory architecture. The LUT memory access operation is sequential in nature and instead of address decoder a ring counter is used to scan the memory contents and gated driver tree structure is implemented to control the clock and data switching activities. The proposed algorithm yields 20% of power reduction than existing.