多进制（Q-ary）LDPC码的编译码原理

多进制(Q-ary)LDPC码是将二进制LDPC码一般化到有限域GF(q),其校验矩阵元素不再是(0,1),而是集合(0,1,…,q-1),其译码仍然采用高效的信度传递迭代译码算法.本文主要阐述了多进制LDPC码的编译码原理,并介绍了一种可简化译码的傅立叶变换译码算法.通过将多进制LDPC码的性能与二进制LDPC码和RS码的性能进行比较,可以看出多进制LDPC码在磁存储系统、下一代ADSL系统以及深空通信方面将是取代RS码的强有力的候选,有极其重要的应用价值.     

影响多进制LDPC码译码性能因素研究

多进制LDPC码是将二进制LDPC码推广到有限域GF(q),其校验矩阵的元素不再是0和1,而是集合(0,1,2,…,q-1),译码仍然采用高效的基于置信度传播的迭代译码算法。文中主要阐述了准循环多进制LDPC码(QC-LDPC)校验矩阵的构造以及最小和译码算法的原理,然后在高斯白噪声信道(AWGN)中,用Matlab了仿真不同条件下LDPC码的译码性能,比较分析了影响多进制LDPC码译码性能的因素。     

带宽有效传输的GF(q)上LDPC编码设计

以Davey(1998)提出的Monte-Carlo方法为基础的、适用于二进制PSK调制的二进制LDPC(Low-Density Parity-Check,低密度奇偶校验)码的最优化理论已经在相关文献中得到了验证。但由于q进制星座没有旋转对称性,因而限制了Davey的方法的应用。本文提出了应用在准正规编码类型上的一种有效的Davey型Monte-Carlo最优化编码设计方法。应用这种方法,可直接将GF(q)上的最优LDPC编码和任意的q进制调制结合起来,获得很高的带宽效率。本文采用MQAM和MPSK调制机制与准正规LDPC编码相结合的若干实例来论证该设计方法。     

多进制LDPC译码算法的研究

多进制LDPC码是将二进制LDPC码推广到有限域GF（q）,其校验矩阵的元素不再是（0,1）,而是集合（0,1,…,q-1）,译码仍然采用高效的基于置信度传播的迭代译码算法。这里主要推导了多进制译码算法的迭代公式,分析证明了基于快速傅里叶变换（FFT）理论的改进算法,最后通过仿真手段验证和分析了基于FFT的多进制译码算法的优越性能。     

不规则LDPC码构造方法研究及其改进

通过对码的度数分布进行设计,非规则LDCP码能获得比规则LDPC码更好的性能,但非规则LDPC码在高SNR区会出现错误平层.在本文中,利用ACE算法,对非规则LDPC码的构造方法PEG算法进行改进,以降低非规则LDPC码的错误平层.最后Matlab模拟证明此算法有效提高了非规则LDPC码在加性高斯白噪声通道中的纠错性能.     

一种光通信系统中基于16-QAM的LDPC编码调制方案

设计了一种适用于16-QAM( quadrature amplitude modulation)系统的LDPC(low density parity check)级联编码调制方案。方案采 用了 本文所设计的一种低复杂度的软解调与二进制LDPC结合的算法,降低译码复杂度并增加方 案的实用性;同时方案 兼容当前OUT-4帧的级联码结构,这样可以利用级联码巧妙有效地解决LDPC码的错误平层问 题。仿真结果表明,本文 提出的LDPC级联编码调制方案,在误码率(BER)为10－8时,较G.709标准中的RS(255,9)的NCG(net code gain) 提高了2.8dB;同时,较ITU-T G.975.1标准 中两种码率相近的RS(255,9)+CSOC(n/k=7/6,J=8) 级联码和正交级联BCH码,在BER为10 －8时, 本文方案的NCG分别提高了1.3dB和0.2dB,且冗余度较两种方 案都低。此外,本文方案实现了3.28bits/symbol的SE (spectra l efficiency)。在BER为10－8时 ,本文方案较频谱效率低 于它的4-QAM、8-QAM以及8-QAM-RS(255,9)分别有着3.5、6.4和2dB的增益 。比较标准中建议的FEC(forward error correction)方案,本文提出的方案在NCG和SE两方面性能上都有所提升。     

LDPC码译码算法及性能分析

为了进一步降低低密度奇偶校验(LDPC)码译码算法的复杂度,基于经典置信传播(BP)译码算法,给出了对数域迭代后验概率对数似然比(APP LLR)算法。通过概率域的和积算法(SPA)和对数域的迭代APP LLR算法的性能仿真及分析可见,迭代APP LLR算法能以较小的性能损失换取复杂度的大幅降低。进一步选用迭代APP LLR算法,结合不同地形条件下的VHF频段信道模型,仿真了LDPC码编译码系统的性能。理论分析及仿真结果均表明,基于迭代APP LLR算法的LDPC码,实现简单,性能优异,具有良好的工程应用前景。     

比特级码率兼容多元LDPC码打孔算法

多元低密度奇偶校验(Non-binary Low-density Parity-check,NB-LDPC)码在中短码情况下性能优于传统二元LDPC码,更接近香农限。针对多元LDPC码码率兼容(Rate-compatible)的问题,提出了一种基于比特级的新型多元打孔算法。首先采用二进制镜像矩阵概念对多元校验矩阵进行映射处理,再根据变量节点的度分布选择合适的打孔节点,从而实现比特级多元LDPC码码率兼容的打孔方案。仿真结果证明与基于符号级的多元打孔算法相比,所提方案的误码率性能在各个码率分别有0.2~0.4 d B的增益。     

多元LDPC码分层译码算法及其在QPSK调制下的应用

文章将二元LDPC码对数域的分层译码算法成功运用在多元LDPC码的译码过程当中。仿真结果表明,在理想加性高斯白噪声信道环境下,QPSK调制时,多元LDPC码分层译码算法的性能明显优于传统的对数域译码算法,因此它可以有效提升消息传递算法的收敛速度,减少译码延时。     

多码率LDPC码高速译码器的设计与实现

低密度奇偶校验码(LDPC码)以其接近香浓极限的性能得到了广泛的应用.如何在.FPGA上实现多码率LDPC码的高速译码,则是LDPC码应用的一个焦点.本文介绍了一种多码率LDPC码及其简化的和积译码算法;设计了这种多码率LDPC码的高速译码器,该译码器拥有半并行的运算结构和不同码率码共用相同的存储单元的存储资源利用结构,并以和算法与积算法功能单元同时工作的机制交替完成对两个码字的译码,提高了资源利用率和译码速率.最后,本文采用该结构在FPGA平台上实现了码长8064比特码率7/8、6/8、5/8、4/8、3/8五个码率的多码率LDPC码译码器.测试结果表明,译码器的有效符号速率达到200Mbps.     

Construction of LDPC codes over GF（q） with modified progressive edge growth

A parity check matrix construction method for constructing a low-density parity-check (LDPC) codes over GF(q) (q>2) based on the modified progressive edge growth (PEG) algorithm is introduced. First, the nonzero locations of the parity check matrix are selected using the PEG algorithm. Then the nonzero elements are defined by avoiding the definition of subcode. A proof is given to show the good minimum distance property of constructed GF(q)-LDPC codes. Simulations are also presented to illustrate the good error performance of the designed codes.     

一种低译码复杂度的Turbo架构LDPC码

针对低密度奇偶校验(LDPC)码较大的译码复杂度和RAM占用,该文提出了一种低译码复杂度的Turbo架构LDPC码并行交织级联Gallager码 (Parallel Interleaved Concatenated Gallager Code,PICGC)。该文给出了PICGC的设计方法和编译码算法,并分析比较了PICGC译码器与LDPC译码器所需的RAM存储量,推导出RAM节省比的上界。理论分析和仿真结果表明,PICGC以纠错性能略微降低为代价,有效地降低译码复杂度和RAM存储量,且译码时延并未增加,是一种有效且易于实现的信道编码方案。     

An Efficient VLSI Architecture for Nonbinary LDPC Decoders

Low-density parity-check (LDPC) codes constructed over the Galois field $ hbox{GF}(q)$, which are also called nonbinary LDPC codes, are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity quasi-optimal iterative decoding algorithms have been proposed, the VLSI implementation of nonbinary LDPC decoders has rarely been discussed due to their hardware unfriendly properties. In this brief, an efficient selective computation algorithm, which totally avoids the sorting process, is proposed for Min–Max decoding. In addition, an efficient VLSI architecture for a nonbinary Min–Max decoder is presented. The synthesis results are given to demonstrate the efficiency of the proposed techniques.      

FPGA implementation of low complexity LDPC iterative decoder

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.     

适于分层译码算法的LDPC码构造方法

The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check (LDPC) decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts, we propose a construction algorithm of LDPC codes, to which a constraint condition is added in the Progressive Edge-Growth (PEG) algorithm. The constraint condition can guarantee that for our constructed LDPC codes, the sets of all the variable nodes connected to the consecutive layers do not share any common variable node, which can avoid the memory access conflicts. Simulation results show that the performance of our constructed LDPC codes is close to the several other LDPC codes adopted in wireless standards. Moreover, compared with the decoder for IEEE 802. 16e LDPC codes, the throughput of our LDPC decoder has large improvement, while the chip resource consumption is unchanged. Thus, our constructed LD-PC codes can be adopted in the high-speed transmission.     

Design and analysis of nonbinary LDPC codes for arbitrary discrete-memoryless channels

We present an analysis under the iterative decoding of coset low-density parity-check (LDPC) codes over GF(q), designed for use over arbitrary discrete-memoryless channels (particularly nonbinary and asymmetric channels). We use a random- coset analysis to produce an effect that is similar to output symmetry with binary channels. We show that the random selection of the nonzero elements of the GF(q) parity-check matrix induces a permutation-invariance property on the densities of the decoder messages, which simplifies their analysis and approximation. We generalize several properties, including symmetry and stability from the analysis of binary LDPC codes. We show that under a Gaussian approximation, the entire q-1-dimensional distribution of the vector messages is described by a single scalar parameter (like the distributions of binary LDPC messages). We apply this property to develop extrinsic information transfer (EXIT) charts for our codes. We use appropriately designed signal constellations to obtain substantial shaping gains. Simulation results indicate that our codes outperform multilevel codes at short block lengths. We also present simulation results for the additive white Gaussian noise (AWGN) channel, including results within 0.56 dB of the unrestricted Shannon limit (i.e., not restricted to any signal constellation) at a spectral efficiency of 6 bits/s/Hz.     

一种兼容Turbo码的LDPC解码器

提出了一种兼容Turbo码的低密度校验码(LDPC)解码器,它可以将Turbo码完全转化为LDPC码来进行解码,由于采用了校验分裂方法来处理由Turbo码转化而来的LDPC码中所存在的短环,从而使其解码性能优于联合校验置信度传递(JCBP)算法0.8 dB,仅仅比Turbo码专用的BCJR算法损失约为1dB.本文提出的通用解码器,为多系统兼容通信设备的应用提供了一种新的、灵活方便的实现途径.