数字锁相环相位噪声分析及仿真研究

数字锁相环作为广泛应用的一种频率合成技术,其相位噪声是关键的技术指标。本文对频率源相位噪声的原理进行了扼要阐述,然后从数字锁相环的相位噪声分析模型出发,讨论了环路带宽内和环路带宽外各部件对输出相位噪声的影响。以数字鉴相器ADF4110设计的锁相环为例,利用ADS软件进行电路仿真,进一步验证了分析结果,为数字锁相环的设计,提高相位噪声性能提供了参考依据。     

基于PLL频率合成器锁相环的降噪技术

随着无线通信技术的发展以及测试仪器小型化的需要,基于PLL频率合成器锁相环的应用也越来越广泛,这就提出了一个如何在此类锁相环中获得低相位噪声信号的问题。本文简要介绍了PLL频率合成器的基本概念、锁相环的噪声源以及基于频率合成器锁相环相位噪声的估算,在此基础上结合理论推导和工程经验提出了改善相位噪声指标的几种技术措施,包括提高鉴相灵敏度和鉴相频率、优化环路滤波器、改善电源滤波等多种手段。实践证明方法可行有效,获得的环路输出信号不但相位噪声指标满足设计要求,而且杂散信号较少且幅度很低,也为其他该类锁相环的设计和调试提供了有益的参考。     

数字锁相环的相位噪声分析

随着信息化社会的发展,数字锁相环越发受研发人员的重视.而相位噪声是衡量数字锁相环性能的关键技术,更是研究的重点.介绍数字锁相环的组成结构和工作原理,建立环路各个模块的相位噪声模型,从闪烁噪声和白噪声的特性入手,定性分析相位噪声的影响因素,并针对电荷泵增益和环路滤波器阻抗对锁相环电路相位噪声的影响进行了仿真,进一步验证了分析结果,为设计高性能的数字锁相环提供理论基础.     

一种高分辨低杂散频率合成方法

针对频率合成器分辨率和范围之间的矛盾及影响频率稳定度的相位噪声问题,提出一种基于两级小数分频锁相环的频率合成方法,该方法以前级小数分频锁相环实现频率高分辨特性;后级小数分频锁相环对输出信号相噪抑制的基础上,实现输出频率范围的扩展;通过在两级小数分频锁相环之间设计窄带锁相环滤波器对前级小数分频锁相环的噪声进行隔离,且窄带锁相环滤波器的鉴相频率根据后级小数分频锁相环分频比的小数值进行切换,实现对频率合成器的小数分频杂散的有效抑制。     

一种基于DDS＋PLL结构的频率合成器的设计

讨论了一种输出频带宽、跳频速度快、相位噪声低、频率分辨率高的频率合成器的设计方法。该设计采用DDS＋PLL结构,在对单片机的输出信号进行电平转换后采用并行数据控制方式对DDS芯片进行置数,并通过仿真软件设计了环路滤波器和DDS后级低通滤波器,改善了输出信号的相位噪声和杂散性能。基于该方法研制实现了输出频率范围为700～1200MHz的宽带频率合成器,实验结果表明该频率合成器输出功率大于＋4dBm,环路锁定时间为14μs,输出信号相位噪声优于-94dBc/Hz@1kHz,近端杂散抑制度大于-59dBc。     

一种DDS／PLL混合型高分辨率频率合成器

本文利用直接数字频率合成器频率分辨率和相位噪声低而锁相环锁率合成器输出频率高和对鉴相输入呈现窄带特性的优点,用ＳＴＥＬ－１１７５ＤＤＳ芯片设计了一个高分辨率正弦信号产生器,并以此推动锁相环进行倍频。通过这种ＤＤＳ／ＰＬＬ混合型频率合成器,得到了中心频率为３８ＭＨｚ的高分辨率正弦信号。本文给出了电路设计过程及测试结果。     

用取样保持鉴相器的数字式频率合成器环路设计

本文在论述频率合成器设计的一般原则与步骤的基础上,从计算合成器输出相位噪声指标入手,来选择环路最佳参数ζ、ω_0,并对一个采用取样保持鉴相器与吞脉冲分频器的典型数字式频率合成器环路进行了详细的工程设计,所使用的方法与步骤对设计其它类型的频率合成器同样适用。     

低成本高性能混合频率合成器的设计

随着移动通信、雷达、测试仪器等领域的快速发展,低成本、高性能、小体积的频率合成器一直是设计的难点.介绍了1种混合频率合成方案,避免了单环通过简单倍频产生的相噪恶化.采用AD9858实现频率高分辨率,利用可变带宽实现环路快速锁定,使用三级不同带宽的滤波器对环路中的相位噪声、谐波分量等进行抑制.通过最后的实验测试,输出信号...     

基于ADF4002的低相噪取样本振设计

本文设计并实现了一种微波锁相环中取样器的本振电路,取样本振以频率合成芯片ADF4002为鉴相器,反馈通道采用内插混频器的结构,避免了单环通过简单倍频产生的相位噪声恶化。详细阐述了取样本振电路的实现方案和工作原理,并使用仿真软件对环路滤波器进行设计。通过实验测试,输出频率为214．815MHz时锁相环的相位噪声为：-137dBc／Hz@10kHz、-140dBc／Hz@100kHz,最大输出频率间隔1MHz,满足了取样本振的低相位噪声和高频率分辨率的要求。     

基于LMX2346集成频率合成器的设计

以LMX2346为核心器件设计频率合成器,介绍了LMX2346的内部结构以及内部每个模块的基本原理,并针对此频率合成器采用三阶无源环路滤波器形式设计了环路参数,利用ADS2008仿真幅频响应图和相位响应图,对LMX2346的控制逻辑图进行详细说明,最后获得测试结果验证了基于LMX2346的频率合成器有较好的相位噪声,达...     

适合集成电路实现的非均匀同步过采样谐波测量算法

从集成电路设计的角度,提出了一种基于非均匀同步过采样技术的谐波测量算法。通过合理设计过采样和降采样2个阶段中非均匀采样时钟频率的概率分布函数,使得频域的非均匀采样噪声可以被忽略。降采样得到的数据可以视为均匀同步采样的结果直接采用快速傅里叶变换进行分析,降低了对分析过程运算能力的要求。利用采样时钟的非均匀特性,大幅简化了延时锁定环路时钟产生电路的复杂度,降低了电路实现代价。仿真结果显示,算法大幅提高了谐波测量的精度。     

皮秒级可调脉宽脉冲码型生成电路设计

针对雷达、通信、电子计量与测试领域对高精度、低噪声、高分辨率、可编程脉冲信号的需求,设计了一种皮秒级可调脉宽脉冲码型生成电路,用于产生脉宽精密可控的多模式多功能系列化脉冲码型信号。该脉冲码型生成电路基于小数分频原理,改变小数分频比将小数杂散移至高频段并由环路低通滤波器滤除,达到降低脉冲信号噪声的目的,在此基础上通过并串转换芯片产生目标信号以及向FPGA提供时钟信号以弥补FPGA本身时钟频率低,精度差的缺点。测试结果表明,脉冲生成电路可产生脉冲频率范围为1mHz～400MHz、最小占空比步进为～的脉冲信号,脉冲信号生成电路输出信号码型可选择归零码、不归零码、归一码、伪随机码等脉冲码型格式的脉冲码型信号。     

A self‐calibrated delay‐locked loop with low static phase error

In conventional delay‐locked loop circuits, the charge and discharge of the charge pump result in mismatched current reflecting the size of the static phase error. The static phase error between feedback clock and reference clock is likely to be within tens or hundreds of picoseconds (ps). We thus propose an approach using digital calibration methods to reduce the charge pump current mismatch by means of the setup time of the D‐type flip flop. The setup time of D‐type flip flop is determined and duplicated to detect the phase error between the reference clock and feedback clock. It results in a very small static phase error between the reference clock and feedback clock. This paper used a 0.18 µm CMOS process design, with a reference frequency of 700 ~ 900 MHz. The active area is 0.031 mm², and the phase error after correction is less than 5 ps. Copyright © 2015 John Wiley & Sons, Ltd.     

Design of a 1‐GSample/s 9‐b double sampling track‐and‐hold amplifier in BiCMOS technology

This paper gives a detail presentation of a fully pseudo‐differential open‐loop BiCMOS track‐and‐hold amplifier (THA) for 9‐b operation up to 1 GSample/s. The proposed THA not only uses a double sampling technique to increase the achievable sampling frequency by a factor of two, but also employs a linearization technique to reduce the gain dependence of the THA input stage upon the input level. Moreover, timing mismatch between the clock signals of the two interleaved paths is minimized by means of a timing mismatch insensitive clock generator controlled by a common master sampling clock. The post‐layout simulation results using TSMC 75 GHz f_T, 0.35‐µm SiGe BiCMOS technology show that the proposed architecture achieve a signal to noise and distortion ratio of 53.92 dB, equivalent to the effective number of bits of 8.66‐b for 58.11 MHz input frequency at 1 GSample/s. The power dissipation of the whole THA is 161.1 mW. Copyright © 2012 John Wiley & Sons, Ltd.     

An experiment on the layout and grounding of power distributionwires in a printed circuit board

An experiment has been designed with the aim to enhance the students' understanding in the topic of conducted electromagnetic interference (EMI). A printed circuit board (PCB) is developed with a motor driver circuit, a digital clock generator, and a sinewave oscillator on board. The digital and analog signals are monitored using an oscilloscope to study the interference effects. The circuit module is duplicated with a different grounding system. A separate ground system proves to be very effective in reducing the conducted EMI. Further noise reduction can be achieved using decoupling capacitors or L-network filters. The effectiveness depends on the location where these additional components are applied. The effect of ground loop is also studied in the experiment     

Long-term stabilization of the optical fiber phase control using dual PID

We propose an approach of long-term stabilization of optical fiber phase by controlling a piezo-based phase modulator and a Peltier component attached to the fiber via a phase-locked loop(PLL) circuit with dual proportional-integral- derivative(PID) adjustment. With this approach, we can suppress the fast disturbance and slow drifting of optical fiber to satisfy the requirements of optical phase long-term locking. In theory, a mathematical model of an optical fiber phase control system is established. The disturbance term induced by environment influence is considered into the PLL model. The monotonous and continuous changing environment disturbance will cause a steady-state error in this theory model. The experimental results accords well with the theory. The steady-state performance, adjusting time, and overshoot can be improved by using the dual PID control. As a result, the long-term, highly stable and low noise fiber phase locking is realized experimentally.     

基于FPGA的一种新型数字鉴频鉴相器的设计

对于电机的锁相控制,需要对相差进行PI性质的环路滤波,但现有的锁相环中鉴频鉴相器输出为相差脉冲而非数字量,难以直接进行PI特性的环路滤波。该文提出了一种基于FPGA的新型数字鉴频鉴相器,通过对晶振时钟的非整数分频获取准确的参考时钟,基于触发器计数机制实现了PFD相差脉冲的数字量化,且可以输出频差数字量。利用VHDL硬件描述语言进行设计,在ModelSim软件中进行仿真,并在EPF10K40型FPGA芯片中进行综合实现,仿真和实验结果验证了该方法的正确性和有效性,为电机锁相控制中环路滤波参数的调整及控制算法的改进提供了便利条件。     

一种改进的脉冲式激光测距仪的设计

脉冲式激光测距仪原理简单,集成化和小型化比较好,采用直接计数激光脉冲延迟时间方法测量距离,精度比较低。本文采用高精度电容的大充放电时间常数比的方法,将待测的微小时间放大,采用较低的时钟精确测量激光脉冲回波与主计数时钟之间小于一个周期的时间间隔,提高了脉冲式激光测距仪的测量精度。本文给出了系统设计框图,实验数据表明,此系统和普通脉冲式激光测距仪相比,距离分辨率提高了20倍。     

Jitter and metastability analysis and modeling of multilevel bang-bang phase detector

Bang-bang phase detector (BBPD) is one of the essential blocks in the phase-locked loop and clock and data recovery that are used in transceivers. But BBPD has the metastability problem as data change in timing window. It suffers from not only metastability failure but also quantization noise, which causes output jitter. In this paper, the novel model is presented to evaluate the effect of both metastability and jitter on ML-BBPD, and also, it is shown that multilevel BBPD (ML-BBPD) has the improved quantization noise in comparison with the Alexander BBPD. In this model, it is shown that by increasing the oversampling ratio, the quantization noise is decreased, and with the metastability effect and the increment of quantization steps, the characteristic curve of the ML-BBPD becomes more smoothed. Also, the output jitter of ML-BBPD, in which metastability failure is diminished, is modeled. The error function in the model is simulated at system level and compares with the results achieved from simulation at circuit level to prove the validity of the proposed model. The simulation is done in TSMC 65-nm CMOS technology under 1-V supply voltage to compare the characteristic of ML-BBPD for various number of sampling clocks.     

A small fully digital open‐loop clock and data recovery circuit for wired BANs

This paper proposes a new open‐loop and low complexity (small size) fast‐lock synchronization circuit for clock and data recovery in wearable systems. The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open‐loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase‐locked loops or delay‐locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non‐return‐to‐zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal‐oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35‐data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption. Copyright © 2015 John Wiley & Sons, Ltd.