High performance white LED driver with single-wire serial-pulse digital dimming

A high performance white light emitter diode (LED) driver based on boost converter with novel single-wire serial-pulse digital dimming (SWSP) is proposed. The driver uses external serial programmed pulses and internal clock to simplify brightness control. By embedding a 5-bit digital analog converter (DAC) into the driver, wide dimming range is achieved. Moreover, a new dynamic slope compensation circuit is presented and other key circuits of the driver are optimized to get higher efficiency and fast transition response. A practical circuit is implemented with 0.6 um bipolar complementary-metal-oxide-semiconductor double-diffused-metal-oxide-semiconductor (BCD) technology. The simulation results show that the driver can provide both wide output current from 1.3 mA to 42 mA with 32-level digital dimming and higher efficiency up to 83% while it works at 1 MHz switching frequency with the input voltage variation from 2.7 V to 5.5 V.     

A multiple-output switched-capacitor DC–DC converter for individual brightness control of RGB LEDs with time-interleaved control and output current regulation

In this paper, an integrated multiple-output switched-capacitor (SC) converter with time-interleaved control and output current regulation is presented. The SC converter can reduce the number of passive components and die areas by using only one flying capacitor and by sharing active devices. The proposed converter has three outputs for individual brightness control of red–green–blue (RGB) LEDs. Each output directly regulates the current due to the V–I characteristics of LEDs, which are sensitive to PVT variations. In the proposed converter, the current-sensing technique is used to control the output current, instead of current-regulation elements (resistors or linear regulators). Additionally, in order to reduce the active area, three outputs share one current-sensing circuit. In order to improve the sensing accuracy, bias current compensation is applied to a current-sensing circuit. The proposed converter has been fabricated with a CMOS 0.13-μm 1P6M CMOS process. The input voltage range of the converter is 2.5–3.3 V, and the switching frequency is 200 kHz. The peak power efficiency reaches 71.8 % at V _IN =2.5 V, I _LED1 = 10 mA, I _LED2 = 18 mA, and I _LED3 = 20 mA. The current variations of individual outputs at different supply voltages are less than 0.89, 0.72, and 0.63 %, respectively.     

宽电压输入可自动均流的PWM型LED驱动器

为了满足LED驱动在宽电压范围内的性能,设计了一种基于Boost-Buck PFC电路的LED驱动器.当输入交流电压变化范围较宽时,PFC的输出依然可以稳定在较低值,可确保功率器件始终保持较小的开关应力.同时,为了满足LED的调光功能,并确保大功率照明场合LED串并联应用的稳定性,各LED并联支路增加了独立调光模块,可根据不同的应用场合工作在独立线性调光、独立PWM调光以及线性PWM复合调光模式,并且通过电流和温度信息的采集各支路可实现自动均流.最后以两路LED并联为基础,搭建实验样机,实现了各支路之间的独立调光以及自动均流.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

Dual-output switched-capacitor DC–DC converter with pseudo-three-phase swap-and-cross control and amplitude modulation mechanism

This paper presents an inductorless dual-output switched-capacitor DC–DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The switched capacitor DC–DC converter was implemented in a standard 0.18-μm 3.3-V CMOS process. Measurements were used to verify that the proposed converter provides dual independently regulated output voltages without cross regulation. The two outputs were regulated at 2.5 and 0.8 V with input ranges of 1.7–2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz, and a maximum power efficiency of 92.1% was achieved for a total output power of 210 mW. The maximal peak-to-peak output ripple voltages for the two outputs at 100 mA load currents were suppressed to below 26 and 20 mV, respectively.     

基于AC/DC数字电源控制器iw1810的LED驱动电路设计

IW1810集成了一个64 kHz的PWM控制器和一个800 V的BJT,该芯片采用数控技术,工作在准谐振模式,提供过流和输出过压保护,简化外围元件确保电路的高效性,无载功率小于100 mW。设计一款基于IW1810高度集成、高效恒流的AC/DC LED驱动电路,电路工作在90 V到264 V的宽电压范围内,输出恒流340 mA,输出功率为4 W,效率高达80%以上,电路板面积仅为18 mm×38 mm。     

基于STM32的多功能LED驱动电源

目前大功率LED照明灯具的驱动电源主要使用集成电路作为电源驱动芯片,其扩展性能差、功能少。针对这些问题,作者基于STM32开发了一种多功能LED驱动电源,通过编程可以实现无级调光与自动温控散热两个扩展功能。测试结果表明：在额定电压为30V、额定电流为3.3A的负载下,输入电压从90V~264V变化时,驱动电源输出电压的波动范围为±1.5V,而输出电流波动范围为±0.11A,恒流特性较好,驱动电源的功率因数均值在0.95以上。     

A 10 Gb/s 0.25 μm SiGe modulator driver for photonic-integration

A 10 Gb/s modulator driver in SiGe 0.25 μm BiCMOS technology with a chip area of only 0.54 mm² is presented. The intentions of designing this modulator driver are to amplify small incoming data signals at 10 Gb/s and to integrate the driver together with a silicon optical phase modulator (Mach–Zehnder modulator in push–pull configuration) on the same chip. The driver is designed to have a low power-consumption of 0.68 W but a high gain (S₂₁ = 37 dB). It consists of a differential pre-amplifier with common-mode feedback and automatic gain control, which is supplied by 2.5 V. The differential output stage is supplied with 3.5 V. The driver is designed to drive a Mach–Zehnder modulator, which uses in his arms carrier depletion in a reverse biased pn junction to adjust the refractive index. The differential output (5V_pp) delivers two times a voltage between 0 and 2.5 V. Therefore no bias-T is needed at the output to assure that the diodes of the interferometer arms are in the reverse biased mode. In addition to the low-power design, a passive network instead of an additional amplifier circuit for driving the cascode transistors, which reduce the collector–emitter voltage of each transistor in the output stage below breakdown, is presented. According to bit-error-ratio (BER) measurements with a pseudo-random-bit-sequence with the length of 2³¹ ? 1 the BER is better than 10^?12 for input voltage differences down to 50 mV_pp. The rise/fall time (20–80 %) is 45/30 ps respectively.     

同步降压DC-DC转换器驱动级设计

提出一种输入电压为4.5～23 V、输出电流可达3A的同步降压转换器的驱动级,内部集成了电平移位、死区时间控制及同步管反向电流限制等功能.设计了一种为内部逻辑供电的低压电源,使驱动级大部分可以由低压器件构成,与外部电源供电的驱动级相比,大大减小了芯片面积.分析了该电路的结构与工作原理;采用0.6 μm BCD工艺,通过HSPICE进行仿真,证明该驱动级方案切实可行.     

一种非隔离型LED照明恒流驱动芯片设计

实现了一种具有超高电压输入、高精度、大调光范围、低成本的非隔离型LED恒流驱动芯片。芯片采用外接高压三极管的电压调整结构以及高精度基准电压源,以PWM峰值电流控制方式实现了高精度、高一致性的电流输出。芯片采用18 V耐压的工艺流片,实现输入电压范围从10 V达到450 V变化,电能转换效率高达92%,驱动电流可从几毫安到超过1 A间设定,电流精度和一致性可达1.5%。     

A transient enhanced DVS DC–DC converter based on state trajectory analysis

Dynamic voltage scaling (DVS) can effectively reduce energy consumption by dynamically varying the supply voltage of the system accordingly to the clock frequency. A new DVS-enabled DC–DC converter is presented in this paper. State trajectory is employed to analyze the transient features of PWM and PFM Buck converters. A novel transient enhancement circuit is designed to improve the transient response of the DVS-enabled Buck converter. To further expand the output voltage range of the converter, a current-starved voltage controlled delay line is proposed in the controller of DC–DC converter to obtain an ultra low voltage of 0.5 V. When the input voltage is 3.3 V, the output voltage of the converter can be dynamically regulated from 0.5 to 2.0 V. The output voltage tracking speed is less than 7.5 μs/V and the recovery speed is 33 μs/A for a load current step from 0.6 to 0.2 A at output voltage of 0.5 V. The chip area is 1.75 mm × 1.33 mm in a 0.18 μm standard CMOS process.     

Freewheel charge-pump controlled single-inductor multiple-output step-up DC–DC converter

This paper presents a freewheel-charge-pump-controlled design for a single-inductor multiple-output (SIMO) DC–DC Converter. By applying the freewheel-charge-pump-controlled (FCPC) technique, the freewheel switching time is reused, and two extra charge-pump outputs are provided by time recycling, with no cost in time sequences. The converter has two step-up outputs and two charge-pump outputs that can be higher or lower than the input supply. The converter utilizes a 1 μH inductor, 4.7 μF charge-pump capacitors and 33 μF output capacitors at a frequency of 1 MHz. The proposed converter shows low cross-regulation and achieves a maximum loading current of 70 mA. Fabricated in a 0.18-μm CMOS process, the proposed circuit occupies 1.3 × 1.3 mm². Experimental results demonstrate that the converter successfully generates four well-regulated outputs with a single inductor. The supply voltage ranged from 1.6 to 2.5 V and the load regulation performance was 0.08, 0.05, 1.7, and 1.9 mV/mA for V_O1, V_O2, V_O3 and V_O4, respectively.     

A high efficiency transmitter and receiver for magnetic resonant wireless battery charging system in 0.35 μm BCD

This paper presents a transmitter and receiver for magnetic resonant wireless battery charging system. In the receiver, a wide-input range CMOS multi-mode active rectifier is proposed for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the configuration of the multi-mode rectifier is automatically selected by switches as original rectifier mode, 1-stage voltage multiplier or 2-stage voltage multiplier mode. As a result, a rectified DC voltage is output from 7.5 to 19 V for an input AC voltage of 5–20 V. In the transmitter, a class-E power amplifier (PA) with an automatic power control loop and load compensation circuit is proposed to improve the power efficiency. The transmitted power is controlled by adjusting the signal applied to the gate of the power control transistor. In addition, a parallel capacitor is also controlled to enhance the efficiency and compensate for the load variation. This chip is implemented using 0.35 μm BCD technology with an active area of around 5,000 × 2,500 μm. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency of the multi-mode active rectifier is about 94 %.The maximum power efficiency of the receiver is about 70 %. The transmitter provides an output power control range of 10–30.2 dBm. The maximum power efficiency of the PA is 71.5 %.     

A fully on-chip 1-μW capacitor-free low-dropout regulator with adaptive output stage

A fully on-chip 1-μW fast-transient response capacitor-free low-dropout regulator (LDO) using adaptive output stage (AOS) is presented in this paper in standard 0.13-μm CMOS process. The AOS circuit is proposed to deliver extra four times of output current of the operational amplifier at medium to heavy load to extend the bandwidth of the LDO and enhance the slew rate at the gate of the power transistor. And the AOS circuit is shut off at light load to reduce the quiescent current and maintain the stability without requiring area-consuming on-chip capacitor. Meanwhile, the proposed AOS circuit introduces V_OUT offset at medium to heavy load to counteract the V_OUT drop, which is caused by I_LOAD increase. Hence, transient performances of LDO and V_OUT drop between light load and full load are improved significantly with 1.1-μA quiescent current at light load. From the post simulation results, the LDO regulates the output voltage at 0.7 V from a 0.9-V supply voltage with a 100-mA maximum load current. The undershoot, the overshoot and the recovery time of the proposed LDO with I_LOAD switching from 50 μA to 100 mA in 1 μs are about 130 mV, 130 mV and 1.5 μs, respectively. And the V_OUT drop between light load and full load reduces to 0.16 mV.     

A flicker-free CMOS LED driver control circuit for visible light communication enabling concurrent data transmission and dimming control

Recent breakthroughs in solid-state lighting technology have opened the door to a variety of applications using light-emitting diodes (LED’s) for not only illumination, but also optical wireless communication. Low-power CMOS technology enables realization of system-on-chip driver circuits integrating multiple functions to control LED device performance, luminance, and data modulation for “intelligent” visible light networking. This paper presents an LED driver circuit architecture, incorporating analog and digital circuit blocks to deliver concurrent dimming control, and data transmission. This is achieved by independent control of output voltage and current using buck converter and current control loops, respectively. This integrated system incorporates the feedback mechanisms to provide uniform light output together with the peak current control, which also prevents flickering. The proposed architecture is flexible enough to take any digital base band modulation format. Designed and implemented in a 180 nm CMOS process, it provides linear 10–90 % dimming control while transmitting data. It also introduces a mechanism which can be applied to the off-the-shelf LED drivers and make them applicable for the visible light communication applications. The power consumption of on-chip circuitry, is negligible compared to the overall power consumption which yields an efficiency of 89 % at 120 mA of load current. The measured bit error rate (BER) varies from 10^?6 at the data rate of 2.5 Mbps to 10^?2 at the data rate of 7 Mbps. All control functions integrated on-chip with the total power consumption of 5 mW.     

A 14-bit 250 kS/s two-step inverter-based incremental $$\varSigma \varDelta$$ ADC for CMOS image sensor in $$0.18\,\upmu \hbox {m}$$0.18μm technology

This paper presents an ultra-low-power, bulk-driven, source-degenerated fully differential transconductor (FD-OTA), operating in subthreshold region. The source-degeneration (SD) and bulk-drive ensure linearity and rail-to-rail input swing. The flipped voltage follower and SD resistor perform V–I conversion in input core with power efficient class AB mode of operation. The reduction in open loop gain and gain bandwidth (GBW) of bulk-drive is compensated by applying partial positive feedback at diode connected MOSFET pair. The current gain from input core to output load side is set (1:1) in OTA₁ and (1:4) in OTA₂. The OTA₂ offers increased transconductance and GBW whereas self-cascode load increases the output impedance and overall gain of the FD-OTAs. Both the input core and common source self-cascode load operate in class AB mode so these FD-OTAs provide enhanced slew rates. These OTAs have been employed to implement Biquadratic low-frequency G_m-C filter suitable for bio-signal applications. The proposed OTA₂ has used dual supply voltage of ± 0.3 V and dissipates around 70 nW power and provides 62 dB FD-open loop gain with GBW of 7.73 kHz while driving the FD-load of 2 × 15 pF. The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuit. The Simulation results verified fully differential total harmonic distortion of ? 72 dB, for 1.2 V_p–p signal at 200 Hz frequency in unity gain configuration with resistive degeneration of 1 MΩ for OTA₁.     

New zero voltage switching DC converter with flying capacitors

A new soft switching converter is presented for medium power applications. Two full-bridge converters are connected in series at high voltage side in order to limit the voltage stress of power switches at V_in/2. Therefore, power metal–oxide–semiconductor field-effect transistors (MOSFETs) with 600 V voltage rating can be adopted for 1200 V input voltage applications. In order to balance two input split capacitor voltages in every switching cycle, two flying capacitors are connected on the AC side of two full-bridge converters. Phase-shift pulse-width modulation (PS-PWM) is adopted to regulate the output voltage. Based on the resonant behaviour by the output capacitance of MOSFETs and the resonant inductance, active MOSFETs can be turned on under zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. Two full-bridge converters are used in the proposed circuit to share load current and reduce the current stress of passive and active components. The circuit analysis and design example of the prototype circuit are provided in detail and the performance of the proposed converter is verified by the experiments.     

A code-pattern-driven digital background calibration technique for SAR ADCs

The article presents the buck converter for the application on headlights of vehicle with chip-level design. The LED components are used as for lighting source, which near/far lights are controlled with high-current switching circuit in the chip. The level-shift circuit and its current driver is proposed to control the input of high-voltage power MOS. The bypass method is presented to reduce the transient time as load current changes suddenly. The input voltage widely ranges from 8 to 21 V while keeping a stable output voltage with 6 V. The chip current can output from 20 to 1500 mA with excellent regulation. This chip had been implemented with TSMC0.25 µm HV- process, and the size of the circuit layout is about 8.6 mm², where includes power switch and far/near lighting switches. Measurements show that peak efficiency can achieve 86.3%. The power regulation is excellent, where the load regulation is only 0.3%, and the line regulation is only 0.5%.

     

全彩128×160液晶显示器驱动电路

该液晶显示器驱动电路由一个 384 通道列驱动电路和一个 160 通道行驱动电路组成.列驱动电路是一个内置 128×3×160×4 bit 显示数据存储器的 128×3 红绿蓝控制器,具有丰富的指令集,内建静态驱动电路指示不同闪速,可使用内置振荡器或输入外部时钟,液晶显示器的建立时间256级可调.行驱动电路有内建的 160 bit双向移位寄存器,支持多种显示模式,内建DC/DC升压电路,驱动电源内建/外接可选.该驱动电路是一个低功耗低输出阻抗的液晶显示控制器.     

CMOS dual output current mode half-wave rectifier

A CMOS dual output current mode half-wave rectifier is presented. The proposed rectifier is composed of three main components: a dual output V–I converter, two half-wave current rectifiers and two I–V converters. A voltage input signal is changed into two current signals by the V–I converter. The current rectifiers rectify these current signals, resulting in positive and negative half-wave current signals that are converted to positive and negative half-wave voltage signals by the I-Vconverters. The theory of operation is described, and the simulated results obtained from the PSPICE program are used to verify the theoretical prediction. Simulated rectifier performance with a 0.5μm MOSFET model using ±1.2V supply voltage demonstrates good rectifier integrity at operating frequencies up to 100MHz.