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1.
基于信息冗余的错误检测与纠正(Error Detection and Correction,EDAC)技术是常见的系统级抗单粒子翻转(Single Event Upsets,SEU)的容错方法,软件实现的EDAC技术是硬件EDAC技术的替代方案,通过软件编程,在现有存储段上增加具有纠错功能的编码(Error-correcting Codes,ECC)来实现存储区错误的检测和纠正。分析了软件EDAC方案中,纠错编码的纠错能力及编码效率、刷新间隔、需保护代码量等因素对可靠性的影响,分析和仿真实验结果表明,对于单个粒子引起的存储器随机错误,提高单个码字的纠错能力及编码效率、增大刷新间隔对可靠性的影响不大,而通过缩短任务执行的代码量来提高刷新间隔,以及压缩需保护代码的总量,对可靠性有较大改进。分析结论能够指导工程实践中,在实现资源、实时性、可靠性之间进行优化选择。 相似文献
2.
D. A. Tran A. Virazel A. Bosio L. Dilillo P. Girard S. Pravossoudovich H.–J. Wunderlich 《Journal of Electronic Testing》2014,30(4):401-413
This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kinds of errors in combinational part of logic circuits and thus, can be combined with advanced SEU protection techniques for sequential elements while reducing the power consumption. The proposed architecture combines different types of redundancies: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error correction. Moreover, it uses a pseudo-dynamic comparator for SET and timing errors detection. Besides, the proposed method also aims to reduce power consumption of fault-tolerant architectures while keeping a comparable area overhead compared to existing solutions. Results on the largest ISCAS’85 and ITC’99 benchmark circuits show that our approach has an area cost of about 3 % to 6 % with a power consumption saving of about 33 % compared to TMR architectures. 相似文献
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The expanded use of field programmable gate arrays (FPGA) in remote, long life, and system-critical applications requires the development and implementation of effective, efficient FPGA fault-tolerance techniques. FPGA have inherent redundancy and in-the-field reconfiguration capabilities, thus providing alternatives to standard integrated circuit redundancy-based fault-recovery techniques. Runtime reliability can be enhanced by using such unique features. Recovery from permanent logic and interconnect faults without runtime computer-aided design (CAD) support can be efficiently performed with the use of fine-grained and physical design partitioning. Faults are localized to small partitioned blocks that have fixed interfaces to the surrounding portions of the design, and the affected blocks are reconfigured with previously generated, functionally equivalent block instances that do not use the faulty resources. This technique minimizes the post-fault-detection system downtime, while requiring little area overhead. Only the finely located faulty portions of the FPGA are removed from use. In addition, the end user need not have access to CAD tools, making the algorithm completely transparent to system users. This approach has been efficiently implemented on a diverse set of FPGA architectures. The algorithm's flexibility is also apparent from the variable emphases that can be placed on system reliability, area overhead, timing overhead, design effort, and system memory. Given user-defined emphases, the algorithm can be modified to specific application requirements. Experiments using random s-independent and s-correlated fault models reveal that the approach enhances system reliability, while minimizing area and timing overhead 相似文献
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SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets caused by high-energy space radiation. Single Event Upset (In order to successfully deploy the SRAM-FPGA based designs in aerospace applications, designers need to adopt suitable hardening techniques. In this paper, we describe novel hybrid time and hardware redundancy (HT&HR) structures to mitigate SEU effects on FPGA, especially digital circuits that are designed with bidirectional ports. The proposed structures that combine time and hardware redundancy decrease the SEU propagation mechanisms among the redundant hard units. Analysis results and fault injection experiments on some standard ISCAS benchmarks and MicroLAN protocol, as a case study over the bidirectional ports, show that the capability of tolerating SEU effects in HT&HR technique increases up to 70 times with respect to solely hardware redundant versions. On average, the proposed method provides 39.2 times improvement against single upset faults and 14.9 times for double upset faults; however it imposes about 14.7% area overhead. Also, for the considered benchmarks, HT&HR circuits become 8.8% faster on the average than their TMR versions. 相似文献
6.
Zhi Tian ;Yang Haigang ;Cai Gang ;Qiu Xiaoqiang ;Shu Yi ;Li Yue ;Cheng Xiaoyan 《电子科学学刊(英文版)》2014,31(4):290-297
In deep sub-micron ICs,growing amounts of on-die memory and scaling effects make embedded memories more vulnerable to reliability problems,such as soft errors induced by radiation.Error Correction Code (ECC) along with scrubbing is an efficient method for protecting memories against these errors.However,the latency of coding circuits brings speed penalties in high performance applications.This paper proposed a "bit bypassing" ECC protected memory by buffering the encoded data and adding an identifying address for the input data.The proposed memory design has been fabricated on a 130 nm CMOS process.According to the measurement,the proposed scheme only gives the minimum delay overhead of 22.6%,compared with other corresponding memories.Furthermore,heavy ion testing demonstrated the single event effects performance of the proposed memory achieves error rate reductions by 42.9 to 63.3 times. 相似文献
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Spin-transfer torque random access memory (STT-RAM) is an emerging storage technology that is considered widely thanks to its attractive features such as low power consumption, nonvolatility, scalability and high density. STT-RAMs are comprised of a hybrid design of CMOS and spintronic units. Magnetic tunnel junction (MTJ) as the basic element of such hybrid technology is inherently robust against radiation induced faults. However, the peripheral CMOS component for sensing the resistance of the MTJs are prone to be affected by energetic particles. This paper proposes low power, nonvolatile and radiation hardened latch and lookup table circuits based on hybrid CMOS/MTJ technology for the next generation integrated circuit devices. Simulation results revealed that, the proposed circuits are fully robust against single event upsets (SEU) and also single event double node upsets (SEDU) that are of the main reliability challenging issues in current sub-nanometer CMOS technologies. 相似文献
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Yangsup Lee Sanghyuk Jung Min Choi Yong Ho Song 《Design Automation for Embedded Systems》2010,14(4):389-413
Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and
shock resistance, it has been widely used as a storage media in embedded and computer system environments. However, there
are many shortcomings in flash memory such as potentially high I/O latency due to erase-before-write and poor durability due
to limited erase cycles. To address these performance and reliability anomalies, many large-scale storage systems use redundancy-based
parallel access schemes such as RAID techniques. However, such redundancy-based schemes incur high overhead due to generating
and storing redundancy information, especially in flash-based storage systems. In this paper, we propose a novel and performance-effective
approach using a redundancy-based data management scheme in flash storage, called Flash-aware Redundancy Array. The proposed
technique not only reduces the redundancy management overhead by performing redundancy update operations during idle periods,
but also provides a preventive mechanism to recover data from unexpected read errors occurring before such redundancy update
operations finish. From the experiments, we found that the proposed technique improves flash-based storage systems by 19%
in average execution time as compared to other redundancy-based approaches. 相似文献
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在空间高能粒子影响下,电路容易发生单粒子翻转,而在电路设计中处于核心地位的有限状态机一旦受到单粒子翻转影响,可能无法进行正常的状态转移,从而导致有限状态机失去数据控制功能。为此,面向独热编码的有限状态机进行了抗单粒子翻转设计,并以航空全双工交换以太网中的入队数据总线控制模块作为验证模型,通过故障注入验证了设计方法的正确性。最后对该设计进行了可靠性评估,结果表明相比于传统的三模冗余加固方法,该方法的失效概率降低了两个数量级,此外还能根据实际需求调整纠正位数。相比于编码方式,该方法采用的逻辑更简单,更便于设计人员的开发和使用,具有较强的实用性。 相似文献
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《Microelectronics Reliability》2015,55(6):863-872
As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated. 相似文献
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一种新型的抗辐射加固锁存器 总被引:2,自引:2,他引:0
Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes. 相似文献
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《Reliability, IEEE Transactions on》2009,58(1):193-201
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Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-event-upset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes. 相似文献
15.
There are many Radiation Hardened by Design (RHBD) architectures presented in the literature to mitigate Single Event Upset (SEU) in a storage element, a latch. Nevertheless, the design of a SEU hardened latch is being continuously improved with respect to reliability, performance, power consumption and area overhead. SEU mitigating techniques by design focus on reducing criticality of sensitive nodes in a latch. Sensitive node(s) in a latch could be an active and/or a high impedance node(s). In this paper, we have classified previously presented SEU hardened by design latch architectures and reviewed SEU mechanisms in selected RHBD latch architectures on Complementary Metal Oxide Semiconductor (CMOS) technology models. Simulation studies using latest fault simulation model have been carried out. Simulation results have revealed some interesting observations described in this paper. Our findings, based on analyses, will provide valuable design inputs for futuristic RHBD latches with advanced technology nodes. 相似文献
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Finite state machine (FSM) is a critical part in digital processing devices used in Internet of Things (IoT) applications as it controls complete functionality of the device. The synthesis tool implements deterministic FSM by adding extra don’t care states/transitions during optimization. This additional insertion makes the FSM vulnerable to setup-time violation based fault injection (STVFI) and hardware Trojan attacks. The existing techniques are inefficient to completely mitigate these vulnerabilities and exhibit significant design overhead. Therefore, this paper presents a novel lightweight secure machine design technique that completely mitigates the vulnerabilities with minimum overhead. The paper first proposes a new metric to identify all types of vulnerable transitions (VTs) followed by a trustworthy FSM design algorithm and efficient vulnerability mitigation architecture (EVMA). Though our EVMA completely alleviates the vulnerabilities to STVFI and Trojan attacks, it slightly increases the overhead due to additional multiplexers. Hence, we also propose new secure FSM design algorithm and two new lightweight vulnerability mitigation architectures (LVMA-I and LIVMA-II) that control the FFs using existing clear and/or preset pins instead of multiplexers. The experimental results on AES and RSA encryption modules show that the proposed technique detects 100% VTs. Further, ASIC and FPGA implementation of the proposed LIVMA-II using Cadence RTL and Xilinx Vivado presents on an average 40%, 59.6%, and 51.1% reduced area, power and delay respectively compared to the well-known technique. Due to negligible design overhead, our technique is best suitable for designing secure controller of portable IoT devices. 相似文献
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针对空间辐照环境,设计了一款基于FPGA平台抗辐照加固嵌入式系统。通过对存储单元进行三模冗余设计和(12,8)汉明码EDAC编码设计进行加固。对MC8051 IP核、I2C IP核、判决器,EDAC编码解码器等模块进行部分动态可重构设计。使用ICAP接口进行回读对比和动态可重构操作。系统配置后,定时对其进行回读对比。当检测到FPGA发生单粒子翻转时,采用部分重配置消除单粒子影响,使系统恢复正常。 相似文献
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With the high flexibility, increasing computing power and lower power consumption, FPGA devices have gained a lot interest in space and avionic applications. Among different types of FPGA devices, Flash-based FPGA is becoming increasingly attractive since their configuration memory is almost immune to Single Event Upset (SEU) induced by energetic particles. However, when applied in such applications, especially long term space missions, the FPGA devices are subject to cumulative ionizing damage, as known as Total Ionizing Dose (TID). The TID may affect the FPGA causing performance degradation and possible eventual permanent damage leading to functional failure. In this paper, we propose a new workflow for analyzing the TID effect on Flash-based FPGA considering the different distributions of TID over the chip and the different impact factors when the configurable logic is programmed to implement different logics in the design. The experimental results show the feasibility of such workflow to be used as assessment tool at early stage of design development. 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2010,18(2):184-193
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《Microelectronics Journal》2015,46(6):551-562
Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented. 相似文献