3D图形流水线像素处理后期的设计和实现

针对3D图形流水线像素处理后期的实时大批量数据处理和存储器读写要求,以及嵌入式系统资源和功耗的特殊性,给出一种像素处理后期的硬件设计方案。设计首先实现所有测试功能,确保各种效果,其次采用了基于屏幕分割渲染的设计思想,减少存储器需求,然后吸收了Early Z算法,尽早抛弃不可见的三角面信息,减少渲染的数据,最后实现了Flip Quad反走样算法,提高图像的质量。模块已经完成了RTL级建模,并在FPGA上通过验证。     

A processor architecture for 3D graphics

The DLX/3DCP architecture that uses a method of parallel processing on 3-D vectors to overcome the problem of the large number of floating-point operations required in 3-D graphics which limits the performance of graphics systems is described. The architecture's design offers general-purpose programmability from the high-level object-oriented language C++ and generates performance expected only from dedicated special-purpose hardware. Results that show the architecture's performance on graphics operations are presented and compared to the performance of other RISC processors     

A trip down the graphics pipeline: pixel coordinates

A general overview of the classic rendering pipeline is given. An examination of some of the problems that come from the use of transformations in the graphics pipeline is initiated. Exemplary transformations to be used in succeeding articles are derived. It is shown that the obvious way to transform normalized device coordinates to pixel space is wrong. The nature of the pixel space is discussed     

An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing

In order to guarantee both performance and programmability demands in 3D graphics applications, vector and multithreaded SIMD architectures have been employed in recent graphics processing units. This paper introduces a novel instruction-systolic array architecture, which transfers an instruction stream in a pipelined fashion to efficiently share the expensive functional resources of a graphics processor. Specifically, cache misses and dynamic branches can cause additional latencies and complicated management in these parallel architectures. To address this problem, we combine a systolic execution scheme with on-demand warp activation that handles cache miss latency and branch divergence efficiently without significantly increasing hardware resources, either in terms of logic or register space. Simulation indicates that the proposed architecture offers 25% better performance than a traditional SIMD architecture with the same resources, and requires significantly fewer resources to match the performance of a typical modern vector multi-threaded GPU architecture.     

Theories for graphics processors in TIPS-1

This paper describes the theoretical aspects of graphics processors in CAD/CAM system TIPS-1. As one of the man-machine interfaces in the CAD/CAM field, computer graphics plays an important role. And this field, computer graphics involves not only image processing with shaded pictures produced by raster scan displays but also sectional and/or perspective view drawing picture by line drawing display. By using TIPS-1 graphics processors, we can get both raster scan and line drawing pictures for the same of modeled 3-D geometry. The following items are considered as the necessary conditions for developing graphics processors.

• • To develop geometric modeling theory.

• • To develop generative geometry pattern processing theory.

• • To implement problem-oriented graphics routines based on above conditions.

How to complete these conditions is described with several figures and graphic outputs.     

A JPEG-like texture compression with adaptive quantization for 3D graphics application

Published online: 2 October 2001     

基于像素聚类的空间变化表面材质建模

针对空间变化表面材质的反射属性提出了一种基于图像的轻量化建模方法.仅需利用消费级手机,在环境光和点光源下分别对平面材质样本拍摄一幅图像,即可计算重建其表面的双向反射分布函数(svBRDFs)参数图、法向量图、切向量图等材质属性.其中对BRDF参数的拟合采用了一种基于像素聚类的策略,即假定具有相似外观和结构特征的像素属于...     

A consistency-free memory architecture for sort-last parallel rendering processors

Current rendering processors are aiming to process triangles as fast as possible and they have the tendency of equipping with multiple rasterizers to be capable of handling a number of triangles in parallel for increasing polygon rendering performance. However, those parallel architectures may have the consistency problem when more than one rasterizer try to access the data at the same address. This paper proposes a consistency-free memory architecture for sort-last parallel rendering processors, in which a consistency-free pixel cache architecture is devised and effectively associated with three different memory systems consisting of a single frame buffer, a memory interface unit, and consistency-test units. Furthermore, the proposed architecture can reduce the latency caused by pixel cache misses because the rasterizer does not wait until cache miss handling is completed when the pixel cache miss occurs. The experimental results show that the proposed architecture can achieve almost linear speedup upto four rasterizers with a single frame buffer.     

SoMMA: A software-managed memory architecture for multi-issue processors

Embedded processors rely on the efficient use of instruction-level parallelism to answer the performance and energy needs of modern applications. Though improving performance is the primary goal for processors in general, it might lead to a negative impact on energy consumption, a particularly critical constraint for current systems. In this paper, we present SoMMA, a software-managed memory architecture for embedded multi-issue processors that can reduce energy consumption and energy-delay product (EDP), while still providing an increase in memory bandwidth. We combine the use of software-managed memories (SMM) with the data cache, and leverage the lower energy access cost of SMMs to provide a processor with reduced energy consumption and EDP. SoMMA also provides a better overall performance, as memory accesses can be performed in parallel, with no cost in extra memory ports. Compiler-automated code transformations minimize the programmer's effort to benefit from the proposed architecture. The approach shows average speedups of 1.118x and 1.121x, while consuming up to 11% and 12.8% less energy when comparing two modified ρVEX processors and their baselines, at full-system level comparisons. SoMMA also shows reduction of up to 41.5% on full-system EDP, maintaining the same processor area as baseline processors.     

GRASP—A 3D graphics system for Pascal users

This paper describes a 3D graphics package ‘GRASP’ implemented in Pascal language and interfaced with the Pascal compiler developed for the DEC PDP-10 machine, by Urs Amman et al. GRASP supports storage tube and raster scan graphics terminals and pen plotters. The package is incorporated as a set of standard procedures into the enhanced Pascal compiler. The various features of the package are presented here and a comparison is made vis-a-vis the other existing 3D graphics packages. GRASP is simple to use and provides a valuable tool for the development of application programs written in Pascal and requiring a graphics capability.     

Synchronous dataflow architecture for network processors

Network processors are programmable, highly integrated communications circuits optimized to provide processing at high data and packet rates. The packet instruction set computer (PISC) architecture is a synchronous dataflow architecture developed for network processors. It uses a deep pipeline that contains two types of processing elements: PISC processors, which perform programmable data manipulation, and I/O processors, which provide access to shared resources such as look-up table memory, hardware accelerators, or coprocessors.     

Scout: a data-parallel programming language for graphics processors

Commodity graphics hardware has seen incredible growth in terms of performance, programmability, and arithmetic precision. Even though these trends have been primarily driven by the entertainment industry, the price-to-performance ratio of graphics processors (GPUs) has attracted the attention of many within the high-performance computing community. While the performance of the GPU is well suited for computational science, the programming interface, and several hardware limitations, have prevented their wide adoption. In this paper we present Scout, a data-parallel programming language for graphics processors that hides the nuances of both the underlying hardware and supporting graphics software layers. In addition to general-purpose programming constructs, the language provides extensions for scientific visualization operations that support the exploration of existing or computed data sets.     

Perceptually optimized 3D graphics

The author uses models of visual perception to remove nonperceptible components of a 3D computer graphics scene and optimize the system's performance. He considers how much detail can be removed from the scene without the user noticing, and how much added benefit these optimizations actually bring     

A model for integrating multimedia information around 3D graphics hierarchies

We present a model for organizing multimedia information especially suitable for applications with three-dimensional content. The model relies on the hierarchical nature of 3D objects, which are utilized as centralizing structure to give coherence to the organization and access of all other medium types. Techniques have been developed to facilitate the manipulation of all medium types through a consistent user interace paradigm. The modeling of space and time constraints as applied to the animation of graphical objects and their synchronization with video has also been explored. Two industrial training applications have been developed to demonstrate the usability of the system.     

Evaluating graphics displays for complex 3D models

This article summarizes a user study of viewing 3D geometry on large-screen display devices. The geometry models the structure of a complex physical object. Our results show that the crispness of a display device (intraframe performance) must be considered along with the speed at which new frames can be computed (interframe performance). It's important to consider crispness from the user's perspective, using values that aren't often published in device specifications. Equally important is the framework for different types of 3D data and the categorization of display technology and techniques     

Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware

The hierarchical Z-buffer is application-invisible and more efficient than the traditional Z-buffer for quickly rejecting hidden geometries. But there are construction and management issues associated with integrating a hierarchical Z-buffer into current graphics hardware. Here we present a two-level hierarchical Z-buffer algorithm, and provide solutions to these issues. Simulation results show that the bandwidth can be reduced by up to 35%. Moreover we propose a dynamic bi-level HZ-buffer compression technique that reduces the buffer size up by to 40%, and for which there is little performance degradation.     

以访存为中心的阵列众核处理器核心流水线设计

传统的流水线设计是以转移指令为中心的,大量逻辑资源被用于提高处理器转移预测的能力,以保证向流水线发射和执行部件提供充足的指令流。在阵列众核处理器中提出了一种以访存为中心的核心流水线设计。通过提高访存装载指令在流水线中的执行优先级,以及访存装载指令的预测执行机制,可以有效减少顺序流水线因访存延迟所带来的停顿,提高流水线性能和能效比。测试结果表明,以4KB容量的装载指令访存地址表为例,访存为中心的流水线设计可以带来8.6%的流水线性能提升和7%的流水线能效比提高。     

A performance study of general-purpose applications on graphics processors using CUDA

Graphics processors (GPUs) provide a vast number of simple, data-parallel, deeply multithreaded cores and high memory bandwidths. GPU architectures are becoming increasingly programmable, offering the potential for dramatic speedups for a variety of general-purpose applications compared to contemporary general-purpose processors (CPUs). This paper uses NVIDIA’s C-like CUDA language and an engineering sample of their recently introduced GTX 260 GPU to explore the effectiveness of GPUs for a variety of application types, and describes some specific coding idioms that improve their performance on the GPU. GPU performance is compared to both single-core and multicore CPU performance, with multicore CPU implementations written using OpenMP. The paper also discusses advantages and inefficiencies of the CUDA programming model and some desirable features that might allow for greater ease of use and also more readily support a larger body of applications.