A BiCMOS Dual-Band Millimeter-Wave Frequency Synthesizer for Automotive Radars

Design and implementation of a millimeter-wave dual-band frequency synthesizer, operating in the 24 GHz and 77 GHz bands, are presented. All circuits except the voltage controlled oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to simplify the reconfiguration of the division ratio inside the phase-locked loop. The 1 mm $, times , $0.8 mm synthesizer chip is fabricated in a 0.18 $mu{hbox{m}}$ silicon-germanium BiCMOS technology, featuring 0.15 $mu{hbox{m}}$ emitter-width heterojunction bipolar transistors. Measurements of the prototype demonstrate a locking range of 23.8–26.95 GHz/75.67–78.5 GHz in the 24/77 GHz modes, with a low power consumption of 50/75 mW from a 2.5 V supply. The closed-loop phase noise at 1 MHz offset from the carrier is less than ${- }$ 100$~$dBc/Hz in both bands. The frequency synthesizer is suitable for integration in direct-conversion transceivers for K/W-band automotive radars and heterodyne receivers for 94$~$GHz imaging applications.      

A 0.65-V 2.5-GHz Fractional-N Synthesizer With Two-Point 2-Mb/s GFSK Data Modulation

We present ultra-low-voltage circuit design techniques for a fractional-N RF synthesizer with two-point modulation which was realized in 90-nm CMOS using only regular ${rm V}_{rm T}$ devices.; the voltage controlled oscillator, phase-frequency detector and charge pump operate from a 0.5 $~$V supply while the divider uses a 0.65$~$V supply. The frequency synthesizer achieves a phase noise better than $-$120 dBc/Hz at 3 MHz, while consuming 6 mW. A calibration technique to equalize the gain between the two modulation ports is introduced and enables phase/frequency modulation beyond the loop bandwidth of the phase-locked loop. Measurement results for 2-Mb/s GFSK modulation are presented.      

A V-Band CMOS VCO With an Admittance-Transforming Cross-Coupled Pair

A novel circuit topology suitable for the implementation of CMOS voltage-controlled oscillators (VCOs) at millimeter-wave frequencies is presented in this paper. By employing transmission line segments to transform the admittance of the additional cross-coupled pair, the proposed LC-tank VCO can sustain fundamental oscillation at a frequency close to the $f _{max}$ of the transistors. Using a standard 0.18 $muhbox{m}$ CMOS process, a V-band VCO is realized for demonstration. The fabricated circuit exhibits a frequency tuning range of 670 MHz in the vicinity of 63 GHz. The measured output power and phase noise at 1 MHz offset are $-hbox{15~dBm}$ and $-hbox{89~dBc}/hbox{Hz}$ , respectively. Operated at a 1.8 $~$V supply voltage, the VCO core and the output buffer consume a total DC current of 55 mA.      

A 125–1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain ($K_v$) and charge-pump (CP) current over C ($I_{CP}/C$), the SSCG can realize not only adaptive bandwidth but also process independence at each operating frequency. The innovative point is the adaptive bandwidth control using $K_v$ and $I_{CP}/C$ calibration. This control enabled a test chip to keep a sharp triangular SSC profile while operating over a wide frequency range (125 to 1250 $~$MHz). The variations of VCO gain and CP current are reduced to one third those of the conventional architecture. At 1250 $~$Mbps (625$~$MHz) the reduction of spectrum peak amplitude is 18.6$~$dB which is 2.3$~$dB better than the reduction obtained without calibration.      

Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture

A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the power dissipation of the regulator being affected. A replica-based regulator introduces a low-frequency pole in its supply-noise transfer function and avoids degradation of supply-noise rejection beyond the regulator-loop's dominant pole frequency. The prototype PLL fabricated in a 0.18 $mu$m digital CMOS process operates from 0.5 to 2.5$~$GHz. At 1.5$~$GHz, the proposed PLL achieves 1.9$~$ ps long-term rms jitter and a worst case supply-noise sensitivity of ${-}$28$~$dB (0.5$~$rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.      

125-GHz Diode Frequency Doubler in 0.13-$mu{hbox {m}}$ CMOS

The first mm-wave Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler built in 130-nm CMOS uses a balanced topology with two shunt Schottky barrier diodes, and exhibits $sim$10-dB conversion loss as well as $-$1.5-dBm output power at 125 GHz. The input matching is better than $-$10$~$dB from 61 to 66 GHz. The rejection of fundamental signal at output is greater than 12 dB for input frequency from 61 to 66$~$GHz. The doubler can generate signals up to 140 GHz.      

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3$sigma $) over the temperature range from $-{hbox{22}},^{circ}{hbox{C}}$ to 85$,^{circ}{hbox{C}}$ . Fabricated in a baseline 65$~$nm CMOS technology, the frequency reference circuit occupies 0.11$ hbox{mm}^{2}$ and draws 34 $ muhbox{A}$ from a 1.2 V supply at room temperature.      

An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC

This paper presents a low power, ultrahigh-speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse sine-weighted DAC and eight 3-bit fine sine-weighted DACs, the core area of the DDS is 3$,times,$ 2.5 mm$^2$ . The maximum clock frequency was measured at 8.6 GHz with a 4.2958 GHz output. The DDS consumes 4.8 W of power using a single 3.3 V power supply. It achieves the best reported phase and amplitude resolutions, as well as a leading power efficiency figure-of-merit (FOM) of 81.1 $~$GHz$cdot$2$^{{rm SFDR}/6}$/W in the mm-wave DDS design. The measured spurious-free-dynamic-range (SFDR) is approximately 45 dBc with a 4.2958 GHz Nyquist output, and 50 dBc with a 4.2 MHz output in the Nyquist band at the maximum clock frequency of 8.6 GHz. Under a 7.2 GHz clock input, the worst-case Nyquist band SFDR and narrow band SFDR are measured as 33 dBc and 42 dBc respectively. The measured phase noise with an output frequency of 1.57 GHz is ${-}$ 118.55 dBc/Hz at a 10 kHz frequency offset with a 7.2 GHz clock input generated from an Agilent E8257D analog signal generator. All the measurements were taken with the chips bonded in a CLCC-52 package.      

A 47 GHz Cross-Coupled VCO Employing High- Island-Gate Varactor for Phase Noise Reduction

A 47 GHz $LC$ cross-coupled voltage controlled oscillator (VCO) employing the high-$Q$ island-gate varactor (IGV) based on a 0.13 $mu{rm m}$ RFCMOS technology is reported in this work. To verify the improvement in the phase noise, two otherwise identical VCOs, each with an IGV and a conventional multi-finger varactor, were fabricated and the phase noise performance was compared. With $V_{DD}$ of 1.2 V and core power consumption of 3.86 mW, the VCOs with the IGV and the multi-finger varactor have a phase noise of $-$95.4 dBc/Hz and $-$91.4 dBc/Hz respectively, at 1 MHz offset, verifying the phase noise reduction with the introduction of the high-$Q$ IGV. The VCO with IGV exhibited an output power of around $-$15 dBm, leading to a FoM of $-$182.9 dBc/Hz and a tuning range of 3.35% (45.69 to 47.22 GHz).      

A 2.4 GHz Low-Power Sixth-Order RF Bandpass $DeltaSigma$ Converter in CMOS

A sixth-order RF bandpass $DeltaSigma$ ADC operating on the 2.4 GHz ISM band, which is suitable for RF digitization is presented. The bandpass loop filter is based on digitally programmable $Gm$ –$LC$ resonators that can be calibrated online to adjust the RF center frequency. By sampling below the input Nyquist frequency, the clock in the system was reduced to 3$~$ GHz, allowing a large reduction of the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40 $~$dB and 62 dB of SNDR and SFDR, respectively, on a 60 MHz bandwidth with 40 mW of power consumption leading to a FoM of 245 GHz/W (4.1 pJ/conversion step). This implementation paves a possible way towards direct RF digitization receiver architectures.      

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2$times$-oversampling phase-tracking CDR, implemented in 90$,$nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of ${pm }{hbox{615~ppm}}$ between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate ${≪} hbox{10}^{-12}$ was verified up to 38 Gb/s using a 2$ ^{7} -$1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s) the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90$~$nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 ${hbox{mm}}^{2}$ .      

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

A 300 nW, 15 ppm/$^{circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

A low-power CMOS voltage reference was developed using a 0.35 $mu$m standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745$~$mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/ $^{circ}$C at best and 15 ppm/$^{circ}$C on average, in a range from ${-}$ 20 to 80$^{circ}$ C. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4–3 V, and the power supply rejection ratio (PSRR) was ${-}$45 dB at 100 Hz. The power dissipation was 0.3 $mu$W at 80$^{circ}$C. The chip area was 0.05 mm$^2$ . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.      

A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators

This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a typical multi-band oscillator. The relation between the coupling coefficient of the transformer load, selection of frequency bands, and the resulting quality factor at each band is investigated. The concept is validated through measurement results from a prototype fabricated in 0.25 $~muhbox{m}$ CMOS technology. The VCO has a measured tuning range of 1.94 to 2.55 GHz for the low frequency range and 3.6 to 4.77 GHz for the high frequency range. It draws a current of 1 mA from 1.8 V supply with a measured phase noise of $-hbox{116~dBc/Hz}$ at 1 MHz offset from a 2.55$~$GHz carrier. For the high frequency band, the VCO draws 10.1 mA from the same supply with a phase noise of $-hbox{122.8~dBc/Hz}$ at 1$~$ MHz offset from a 4.77 GHz carrier.      

A Low Voltage Mixer With Improved Noise Figure

A 5.2 GHz low voltage mixer with improved noise figure using TSMC 0.18 $mu$m CMOS technology is presented in this letter. This mixer utilizes current reuse and ac-coupled folded switching to achieve low supply voltage. The noise figure of the mixer is strongly influenced by flicker noise. A resonating inductor is implemented for tuning out the parasitic components, which not only can improve noise figure but also enhance conversion gain. A low voltage mixer without resonating technique has also been fabricated and measured for comparison. Simulated results reveal that flicker corner frequency is lowered. The measured results show 4.5 dB conversion gain enhancement and 4 dB reduction of noise figure. The down-conversion mixer with resonating inductor achieves 5.8 dB conversion gain, ${-}16$ dBm ${rm P}_{{rm 1dB}},$ ${-}6$ dBm ${rm IIP}_{3}$ at power consumption of 3.8 mW and 1 V supply voltage.      

Integrated Quadrature Couplers and Their Application in Image-Reject Receivers

Several fully-integrated multi-stage lumped-element quadrature hybrids that enhance bandwidth, amplitude and phase accuracies, and robustness are presented, and a fully-integrated double-quadrature heterodyne receiver front-end that uses two-stage Lange/Lange couplers is described. The Lange/Lange cascade exploits the inherent wide bandwidth characteristic of the Lange hybrid and enables a robust design using a relatively low transformer coupling coefficient. The measured image-rejection ratio is $>$ 55 dB over a 200 MHz bandwidth centered around 5.25 $~$GHz without any tuning, trimming, or calibration; the front-end features 23.5 dB gain, $-$79 dBm sensitivity, 5.6 dB SSB NF, $-$7$~$ dBm IIP3, $-$18 dB $S_{11}$ and a 1 mm $times$ 2 mm die area in 0.18$ mu{hbox {m}}$ CMOS.      

A 167-Processor Computational Platform in 65 nm CMOS

A 167-processor computational platform consists of an array of simple programmable processors capable of per-processor dynamic supply voltage and clock frequency scaling, three algorithm-specific processors, and three 16 KB shared memories; and is implemented in 65 nm CMOS. All processors and shared memories are clocked by local fully independent, dynamically haltable, digitally-programmable oscillators and are interconnected by a configurable circuit-switched network which supports long-distance communication. Programmable processors occupy 0.17$ hbox{mm}^{2}$ and operate at a maximum clock frequency of 1.2 GHz at 1.3 V. At 1.2 V, they operate at 1.07 GHz and consume 47.5$~$mW when 100% active, resulting in an energy dissipation of 44 pJ per operation. At 0.675 V, they operate at 66 MHz and consume 608$ muhbox{W}$ when 100% active, resulting in a total energy dissipation of 9.2 pJ per ALU or MAC operation.      

A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology

A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 $mu{rm m}$ RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit $(FOM_{1})$ and the tuning-range figure of merit $(FOM_{2})$ are optimal at 12.79 dB/mW and 2.6 ${rm mW}^{-1}$, respectively. The chip area is 0.89 $,times,$0.89 ${rm mm}^{2}$.      

A Fully Integrated 0.13- $mu$m CMOS 40-Gb/s Serial Link Transceiver

A fully integrated 40-Gb/s transceiver fabricated in a 0.13-$mu$m CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low ${rm f}_{rm T}$ of 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4$, times ,$2.9 mm$^{2}$ with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2$^{15}-1$ PRBS data is 1.85 ${rm ps}_{rm rms}$ over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 ${rm ps}_{rm rms}$ and the measured BER of the transceiver is less than $10^{- 14}$ .      

A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop

This paper introduces a pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostly-digital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demonstrated with a prototype consisting of a custom 0.13 $mu$m integrated circuit with active area of 0.4 mm$^{2}$ and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur, and estimated deterministic jitter of 130 fs (rms), ${-}$ 63.9 dBc, and 200$~$ fs (peak-to-peak), respectively.