运载火箭时序仿真测试系统设计

检测运载火箭地面测试设备的方法种类繁多,方法复杂,测试周期较长。设计一种运载火箭时序仿真测试系统,采用FPGA芯片的SOPC(可编程片上系统)技术,基于全双工USB 3.0控制芯片( CYUSB3014)完成上位机通信,单板模拟运载火箭飞行过程中64路时序系统发出的时序信号和时串信号,对不同测试需求的地面测试设备进行功能检测和故障诊断。具有方法简单,通用性好、精度等级高、通道数多的优点,能有效提高地面测试设备在测试任务中的测试效率。     

基于双FPGA的刀闸接口控制箱的设计

现有变电站改造成数字化变电站时需要增加过程层设备,其中对刀闸接口控制箱的动作可靠性提出了极高的要求。提出一种基于双FPGA实现多重逻辑闭锁的刀闸接口控制箱实现方案。设计了FPGA电源和时钟实现电路,两块FPGA的信息交换方式以及逻辑互锁方法。详细描述了出口电路自检方案。介绍FPGA配置和编程方法,给出了FPGA的时序仿真。测试了电源建立波形,实现并验证了装置运行的可靠性。该方案能够有效防止误动作发生,适用于有此需求的一般装置。     

电梯安全部件检测中提高砝码装卸效率的方法研究

本文作者从事电梯安全部件检测工作多年,结合自身经验,研制出一款用于电梯安全部件检测设备中的砝码装卸装置,该装置可实现砝码的快速简便装载,操作灵活,适用于单个砝码质量大的场合,在降低由于砝码装卸不均匀或不牢固对测试结果影响的同时,且可有效保障操作人员的安全性。     

某搜索雷达天线座专用检测设备设计

雷达天线座作为雷达系统重要组成部分之一，对保障雷达系统正常工作起着关键作用。为了保证雷达天线座出现故障时能够进行快速维修，本文针对某搜索雷达天线座设计了一款专用检测设备。首先通过提出该检测设备主要功能的需求，然后设计了力矩测试装置和编码测试装置等组成部件，最后进行了试验，验证了这款专用检测设备的可靠性，能够有效提高该雷达天线座的维修效率。     

基于FPGA的中尺寸数字TFT—LCD测试装置设计

介绍了一种以FPGA为核心器件的中尺寸数字TFT-LCD 面板测试装置的硬软件设计方案及实现,重点描述了驱动时序发生、VCOM和Gamma参考电压产生以及按键PWM调光功能模块的硬软件设计.通过软件时序仿真及实验验证,该测试装置能清晰、稳定地显示单色、灰阶、Cross-Talk 和Flicker等常见的TFT-LCD测试画面,具有使用灵活、通用性好和可移植性强的优点,能很好地满足实际生产中不良品检测、光学性能测试与分析的需要.     

配电网新型一二次融合系统测试平台设计与研究

为了实现对配电网一二次融合系统的测试和控制功能进行检测,设计了一种能够对配电网一二次融合系统工作环境进行模拟检测的新型测试平台。首先介绍了智能化配电网电气设备一次、二次设备深度融合的总体框架和实现方法;在此基础上,通过配置文件和物理设备来分析和设计系统的测试平台,可实现一二次融合系统的动作逻辑、高级应用等进行闭环测试。测试结果表明：设计的测试平台能够对配电网一二次融合系统的工作环境进行模拟,在配电网一二次融合系统入网检测、工程调试中发挥了重大作用,具有重大的电网实际工程应用价值。     

基于PLC的涡流检测装置控制设计

提出了涡流检测装置的控制分析与设计,分析了涡流检测装置的工作原理,完成了PLC对步进电机和气动系统的合理控制,目前该装置对产品的检测中各部分协调性良好。本检测装置通过PLC有效地将机、电和气结合起来,在汽车轮毂等转轴零件的检测中取得了很好的效果,这将有助于其他同类检测设备的研制开发。     

航空机载设备中可编程逻辑器件的第三方测评方法研究

目前航空机载设备中可编程逻辑器件的应用领域和规模逐步扩大,在设备软件测评过程中软件测试人员面临着是否需要对FPGA/CPLD进行测试、如何测试的困惑。针对该疑问,本文对传统的软件测试方法和可编程逻辑器件验证方法进行分析,并借鉴军用产品软件第三方测评进入条件评估的思路,提出了能够较好地适应高安全性设备软件第三方测评的流程和方法,提高可编程逻辑器件测评的效率。     

基于DSP的声磁EAS系统设计

针对射频EAS系统的低检测灵敏度、高误报率等缺陷,设计了一种基于DSP的声磁EAS系统。阐述了系统检测装置的硬件结构及工作时序,分析了声磁标签信号的特征,提出了一种声磁标签信号的检测方法。经过实验测试,系统的抗干扰性能、检测率、误报率等特性都比射频系统有显著的改善。     

基于FPGA的ARM并行总线研究与仿真

通过EP2C20Q240器件和LPC2478处理器,研究ARM应用系统外部并行总线的工作原理和时序特性,以及在FPGA中进行双向总线设计的原则,设计并实现了FPGA并行总线。借助Quartus II仿真工具,对FPGA并行总线进行了时序仿真,并用SignalTap II逻辑分析仪进行在线测试,验证设计的正确性。     

概率时态认知逻辑模型检测中三值抽象技术的研究

 为缓解概率时态认知逻辑模型检测中的状态空间爆炸问题,提出了概率时态认知逻辑的三值抽象技术.具体研究内容包括:定义抽象模型及模型上概率时态认知逻辑的三值语义,依据状态空间等价划分建立初始抽象模型,并证明抽象技术对概率时态认知逻辑的满足性保持关系;提出概率时态认知逻辑模型检测算法;依据初始模型检测的结果,给出利用最小证据和最小反例引导的抽象系统的求精过程.最后通过Dining Cryptographer协议说明了抽象技术的应用,及其在约简系统状态空间方面的效果.     

一种基于区间时序逻辑模型检测的入侵检测算法

Model checking based on linear temporal logic reduces the false negative rate of misuse detection. However, linear temporal logic formulae cannot be used to describe concurrent attacks and piecewise attacks. So there is still a high rate of false negatives in detecting these complex attack patterns. To solve this problem, we use interval temporal logic formulae to describe concurrent attacks and piecewise attacks. On this basis, we formalize a novel algorithm for intrusion detection based on model checking interval temporal logic. Compared with the method based on model checking linear temporal logic, the new algorithm can find unknown succinct attacks. The simulation results show that the new method can effectively reduce the false negative rate of concurrent attacks and piecewise attacks.     

多输出电路跳变次数(TC)测试算法

本文提出了一种多输出电路的改进TC测试法。该方法根据多输出电路的输入输出的函数关系把电路按输出分解，然后按照各个输出的相关输入，分别测试输出的响应，从而可以实现对多输出电路的测试，进而说明这种检测的完备性，进一步提出了一种加速测试的方法。     

关键字驱动的自动化测试框架设计与实现

为了提高软件自动化测试脚本的可复用性,本文提出了一种基于关键字驱动的自动化测试框架。框架以关键字驱动思想为核心,在设计自动化测试平台的过程中实现了测试逻辑、测试脚本和测试数据的分离,仅通过对控制文件的修改就可以实现相应测试,同时,测试脚本不关心测试用例,测试的数据和业务逻辑都集成在测试数据表格之中,测试的设计就简化为测试数据表格的设计,最大程度地减少了相互之间的影响。进一步把测试工程师从繁琐的重复性劳动中解放出来,为软件产品提供更为高效的、精准的测试,提高产品的竞争力。     

Intelligent Analysis and Off-Line Debugging of VLSI Device Test Programs

Today's microelectronics researchers design VLSI devices to achieve highly differentiated devices, both in performance and functionality. As VLSI devices become more complex, VLSI device testing becomes more costly and time consuming. The increasing test complexity leads to longer device test programs development time as well as more expensive test systems, and debugging test programs is a great burden to the test programs development. On the other hand, there is little formal theory of debugging, and attempts to develop a methodology of debugging are rare. The aim of the investigation in this paper is to create a theory to support analysis and debugging of VLSI device test programs, and then, on the basis of this theory, design and develop an off-line debugging environment, OLDEVDTP, for the creation, analysis, checking, identifying, error location, and correction of the device test programs off-line from the target VLSI test system, to achieve a dramatic cost and time reduction. In the paper, fuzzy comprehensive evaluation techniques are applied to the program analysis and debugging process to reduce restrictions caused by computational complexity. Analysis, design, and implementation of OLDEVDTP are also addressed in the paper.     

Instrumentation for mapping light intensity contours

Automobile headlamp illumination is of concern because uniformity and shape of the beam pattern are quite important for optimum road visibility and safety for oncoming drivers. The Society of Automotive Engineers' specification on headlamp illumination [1] designates the maximum and minimum intensities at several spots within the beam. Many states require inspection of vehicle-mounted headlamps for illumination and aiming, and this test is commonly performed using a device which clamps on the headlamp lens. This clamp-on device is limited to checking the maximum intensity at beam center, rather than checking the overall beam pattern to the SAE-J579a specifications. In addition, mechanical limitations of this device have often resulted in the mis-aiming of vehicle headlamps. Present instrumentation available for measuring light intensity per SAE-J579a is primarily of the photo-cell type device, and the point-to-point measurement of light intensities is quite tedious and time consuming. A technique is described in this paper which incorporates electronic signal processing into a closed-circuit television system for displaying contours of constant illumination intensity. The technique is capable of rapidly performing vehicle-mounted headlamp testing per SAE-J579a and could be adapted for use at state inspection stations.     

Highly testable design of BiCMOS logic circuits

Most of the work reported in the literature to date on the testability of BiCMOS circuits has concentrated on fault characterization and the need for a suitable testing method that can address the peculiarities of BiCMOS circuits. The problem of adequately testing large BiCMOS logic networks remains open and complex. In this paper, we introduce a new design for testability technique for BiCMOS logic gates that results in highly testable BiCMOS logic circuits. The proposed design incorporates two features: a test charge/discharge path and built-in current sensing (BICS). The test charge/discharge path is activated only during testing and facilitates the testing of stuck-open faults using single test vectors. BICS facilitates testing of faults that cause excessive IDDQ. HSPICE simulation results show that the proposed design can detect stuck-open faults at a test speed of 10 MHz. Faults causing excessive IDDQ are detected by BICS with a detection time of 1 ns and a settling time of 2 ns. Impact of the proposed design on normal operation is minimal. The increase in propagation delay in normal operation is less than 3%. This compares very favorably with CMOS BICS reported in the literature, where the propagation delay increase was 20%, 14.4% respectively. The increase in the area is less than 15%     

单边多输出逻辑函数补集软件的设计与实现

根据单边逻辑函数的特性，介绍了一种多输入多输出单边逻辑函数补集方法，该方法采用二进制特征矩阵和状态矢量来描述原函数，进行最小列覆盖的选择形成多输出补集函数的控制矩阵，由控制矩阵与补集函数的状态矢量形成单边单输出补集合逻辑函数，通过多输出逻辑函数分解与合并最终产生多输出单边逻辑函数的补集。所设计的多输入多输出单边逻辑函数补集算法软件，在P-1．8GHz，512MBRAM的计算机上完成测试和运行。并通过测试检验程序，保证输出结果在逻辑上与输入条件求补等价。     

Application-Dependent Testing of FPGAs

Testing techniques for interconnect and logic resources of an arbitrary design implemented into a field-programmable gate array (FPGA) are presented. The target fault list includes all stuck-at, open, and pair-wise bridging faults in the mapped design. For interconnect testing, only the configuration of the used logic blocks is changed, and the structure of the design remains unchanged. For logic block testing, the configuration of used logic resources remains unchanged, while the interconnect configuration and unused logic resources are modified. Logic testing is performed in only one test configuration whereas interconnect testing is done in a logarithmic number of test configurations. This approach is able to achieve 100% fault coverage