A novel full-wave rectifier/sinusoidal frequency doubler topology based on CFOAs

In this paper, a high-efficiency class-F power amplifier (PA) is designed using integration between a low voltage p-HEMT transistor and a miniaturized microstrip suppressing cell. It results in nth harmonic suppression and high power added efficiency (PAE) under low radio frequency (RF) input powers. The simulation is performed based on harmonic balance analysis. The proposed power amplifier is fabricated, and measurements results validated the simulations. The proposed power amplifier operates at 1.8 GHz with 100 MHz bandwidth and an average PAE of 71.1%, with very low drain voltage of 2 V. At fundamental frequency of 1.8 GHz, the maximum measured PAE is 73.5% at about 12 dBm RF input power. The maximum output power and gain are 23.4 and 17.5 dBm in RF input power ranges of 0–12 dBm, respectively. The fabricated class-F PA with such characteristics can be used for power amplifications in wireless transmitters such as 4G (4th generation)-LTE (long term evolution) communication systems.     

应用于4G-LTE无线通信系统的F类高PAE射频功率放大器

为了有效实现高谐波抑制并提高功率附加效率,提出了一种适用于4G-LTE无线通信系统的高效F类功率放大器。该功率放大器使用了低电压p-HEMT晶体管和小型微带抑制单元,能够在低射频输入功率下产生n次谐波抑制和较高的功率附加效率（power added efficiency,PAE）。采用谐波平衡法对提出的功率放大器进行了仿真分析,并对其进行了实际制造。通过实际测量对仿真结果进行了验证。测量结果显示,提出功率放大器的工作频率为1.8 GHz,带宽为100 MHz,平均PAE为76.9％,且具有2V的极低漏极电压。射频输入功率范围分别为0-12 dBm时,最大输出功率和增益分别为23.4和17.5 dBm。     

Effects of output harmonic termination on PAE and output power of AlGaN/GaN HEMT power amplifier

The authors experimentally investigate and discuss the effects of output harmonic termination on power added efficiency (PAE) and output power of an AlGaN/GaN high electron mobility transistor (HEMT) power amplifier (PA). The AlGaN/GaN HEMT PA with gate periphery of 1 mm was built and tested at L-band. Large-signal measurements and comparisons of the PAE and output power were carried out at different DC bias conditions from 50% of saturated drain current (I/sub dss/) to 1% of Id., for the PA with and without output harmonic termination. For class-AB operation at 25% of I/sub dss/, an increase of about 10% in peak PAE and 1 dBm in output power were observed in saturated output power range. Improvements of up to 9% in PAE and 1.2 dBm in output power were achieved over the measured DC bias conditions provided the output harmonics are properly terminated.     

A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

In this letter, a fully integrated 20-dBm RF power amplifier (PA) is presented using 0.25-mum-gate silicon-on-sapphire metal-oxide-semiconductor field-effect transistors (MOSFETs). To overcome the low breakdown voltage limit of MOSFETs, a stacked FET structure is employed, where transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the optimum load impedance for a 20-dBm PA increases to 50Omega, which is nine times higher than that of parallel FET topology for the same output power. Measurement of a single-stage linear PA shows small-signal gain of 17.1 dB and saturated output power of 21.0dBm with power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access modulated signal, the PA shows an average output power of 16.3 dBm and PAE of 18.7% with adjacent channel power ratio below -42dBc     

Dual-time resolution time-based transceiver for low-power serial interfaces

This paper presents the design and analysis of a CMOS power amplifier (PA) with active 2nd harmonic injection at the input. In this circuit, the main amplifier operates in class-A to provide a high linearity performance, and the auxiliary one is a class-C high efficiency amplifier, which injects the 2nd harmonic into the main amplifier. Theoretical analysis and simulations show that the proposed technique improves the PA linearity, power added efficiency (PAE), and the output power. The auxiliary amplifier, also referred as injection amplifier, injects the 2nd harmonic to the main (core) amplifier in order to compensate the gain compression phenomena at the main amplifier output node. Moreover, waveform shaping is employed to decrease the overlap of voltage and current waveforms, resulting in PAE improvement. The fully integrated PA with 2nd harmonic injection was designed and simulated in 0.18 µm CMOS technology, with a center frequency of 2.6 GHz. Post-layout simulation of PA exhibits 31.25% PAE in maximum linearity point (1 dBC point), illustrating 12.3% improvement at this power level. The 1 dBC point of PA is improved by 3.2 dB, and the PA output power is 20.2 dBm using 3.3 V supply voltage.     

基于GaN HEMT的高线性星载Doherty功率放大器设计北大核心CSCD

在射频通信链路中,功率放大器决定了发射通道的线性、效率等关键指标。卫星通信由于是电池供电,对功率放大器的工作效率要求比较高。文章基于GaN HEMT晶体管采用对称设计完成了一款高效率的Doherty功率放大器。测试结果表明:该Doherty功放的功率增益大于29 dB;1 dB压缩点功率(P_(1 dB))大于35 dBm;在35 dBm输出时,其功率附加效率(PAE)大于47.5%,三阶交调失真(IMD3)大于35 dBc;在功率回退3 dB时,其PAE大于37%,IMD3大于32 dBc。     

A +31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications

A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky lambda/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8times3.2mm² including all pads and bypass capacitors     

Analysis and design of high-power and efficient,millimeter-wave power amplifier systems using zero degree combiners

We present the analysis and design of high-power millimetre-wave power amplifier (PA) systems using zero-degree combiners (ZDCs). The methodology presented optimises the PA device sizing and the number of combined unit PAs based on device load pull simulations, driver power consumption analysis and loss analysis of the ZDC. Our analysis shows that an optimal number of N-way combined unit PAs leads to the highest power-added efficiency (PAE) for a given output power. To illustrate our design methodology, we designed a 1-W PA system at 45 GHz using a 45 nm silicon-on-insulator process and showed that an 8-way combined PA has the highest PAE that yields simulated output power of 30.6 dBm and 31% peak PAE.     

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-$mu$ m 2.5-V standard I/O FETs in a 0.13- $mu$m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.      

A Handset Power Amplifier With High Efficiency at a Low Level Using Load-Modulation Technique

A new monolithic-microwave integrated-circuit power amplifier for cellular handsets has been implemented using the load-modulation concept of the Doherty amplifier, which has a high efficiency at a low power level. In order to get a compact module, the$lambda/4$transmission line for the load modulation is replaced by a passive high-pass$pi$-network, and the load-modulation circuit is also modified to function as a power-matching circuit of the main amplifier. The amplifier has two modes of operation, low- and high-power modes, controlled by a control voltage. At the high power mode, both the main and auxiliary amplifiers are operational and, at the low power mode, only the main amplifier generates output power enhancing the efficiency. For the code-division multiple-access environment, the amplifier at the low-power mode provides power-added efficiency (PAE) of 39.8% and an adjacent channel power ratio (ACPR) less than 49.8 dBc at 23.1 dBm, and the high-power mode PAE of 37.9% and ACPR of 46.4 dBc at 28 dBm. The efficiency is improved by approximately 18.8% at$ P_ out=23$dBm by the load-modulation technique. For the advanced mobile phone system-mode operation, the amplifier delivers 26.1 dBm with PAE of 53% and 30.8 dBm with 48.7% at the low and high modes, respectively.     

A Wideband 77-GHz, 17.5-dBm Fully Integrated Power Amplifier in Silicon

A 77-GHz,$+$17.5 dBm power amplifier (PA) with fully integrated 50-$Omega$input and output matching and fabricated in a 0.12-$muhbox m$SiGe BiCMOS process is presented. The PA achieves a peak power gain of 17 dB and a maximum single-ended output power of 17.5dBm with 12.8% of power-added efficiency (PAE). It has a 3-dB bandwidth of 15 GHz and draws 165 mA from a 1.8-V supply. Conductor-backed coplanar waveguide (CBCPW) is used as the transmission line structure resulting in large isolation between adjacent lines, enabling integration of the PA in an area of 0.6$hbox mm^2$. By using a separate image-rejection filter incorporated before the PA, the rejection at IF frequency of 25 GHz is improved by 35 dB, helping to keep the PA design wideband.     

一种输出匹配可调的、高线性度宽带功率放大器

采用自适应偏置技术和有源电感实现了一款输出匹配可调的、高线性度宽带功率放大器(PA)。自适应偏置技术抑制了功放管直流工作点的漂移,提高了PA的线性度。有源电感参与输出匹配,实现了输出匹配可调谐,该策略可调整因工艺偏差、封装寄生造成的输出匹配退化。利用软件ADS对电路进行验证,结果表明,在4 GHz频率下,输入1dB压缩点(Pin 1dB)为-7dBm,输出1dB压缩点(Pout 1dB)为11dBm,功率附加效率(PAE)为8.7%。在3.1GHz~4.8 GHz频段内,增益为(20.3±1.1)d B,输入、输出的回波损耗均小于-10dB。     

基于GaN 的3. 4~ 3. 6 GHz 高增益Doherty 功率放大器

基于两级功率放大器架构,设计了一款平均输出功率为37 dBm(5 W)的高增益Doherty 功率放大器。 该器件通过增加前级驱动功率放大器提高Doherty 功率放大器的增益,采用反向Doherty 功率放大器架构,将λ/4 波 长传输线放置在辅助功放后端,相位补偿线放置在主功放前端,并使主功放输出匹配网络采用双阻抗匹配技术实现 阻抗变换,如此可扩宽功率放大器的工作带宽。连续波测试结果显示:3. 4~3. 6 GHz 工作频段内,饱和输出功率在 44. 5 dBm 以上,功率饱和工作点PAE 在43. 9%以上;在平均输出功率(37 dBm,5 W)工作点,回退量大于7. 5 dB,功 率附加效率PAE 为36. 8%以上,功率增益在31 dB 以上。     

A 60 GHz SiGe-HBT Power Amplifier With 20% PAE at 15 dBm Output Power

A monolithic power amplifier (PA) operating in the 60 GHz band is presented. The circuit has been designed utilizing an advanced 0.25 SiGe-heterojunction bipolar transistor (HBT) technology, featuring npn transistors with and . A two-stage cascode architecture has been chosen for the implementation. Design techniques and optimization procedure are explained in detail. Measurements show a small signal gain of 18.8 dB and an output power of 14.5 dBm under 1 dB gain compression at 61 GHz. At this frequency, the saturated output power is 15.5 dBm and the peak power added efficiency (PAE) is 19.7%. To our knowledge, this is the highest PAE reported so far for a monolithic 61 GHz PA in SiGe-HBT technology.     

An InGaP-GaAs HBT MMIC smart power amplifier for W-CDMA mobile handsets

We demonstrate a new linearized monolithic microwave integrated circuit smart power amplifier of extraordinary high power-added efficiency (PAE), especially at the most probable transmission power of wide-band code-division multiple-access handsets. A PAE of 21% at 16 dBm of output power, which is the maximum bound of the most probable transmission power in IS-95 systems, was obtained, as well as 40% at 28 dBm, the required maximum output power, with a single-chip MMIC power amplifier. The power amplifier has been devised with two InGaP-GaAs heterojunction bipolar transistor amplifying chains parallel connected, each chain being optimized for a different P/sub 1dB/ (1-dB compression point) value: one for 16 dBm for the low-power mode, targeting the most probable transmission power, and the other for 28 dBm for the high-power mode. The high-power mode operation shows 40% of PAE and -30 dBc of adjacent channel leakage power ratio (ACLR) at the maximum output power of 28 dBm. The low-power mode operation exhibits -34 dBc of ACLR at 16 dBm with 14 mA of a quiescent current. This amplifier improves power usage efficiency and, consequently, the battery lifetime of the handset by a factor of three.     

High efficiency, wide dynamic range variable gain and poweramplifier MMICs for wideband CDMA handsets

A linearized variable gain amplifier (VGA) and a two-stage power amplifier (PA) MMIC were developed for 1.95-GHz wideband CDMA (W-CDMA) handsets application. A complete PA block with power control ability was obtained by cascading the VGA with the PA. The linearized VGA consists of a predistorter (PD) integrated with a conventional VGA, performing dual function for achieving high linearity power control, as well as reducing output distortion level of the following PA. With the use of predistortion, the P_out and power added efficiency (PAE) of the PA block improved from 27.5 dBm and 39.8% to 28.5 dBm and 44.8%, respectively, measured at -35 dBc adjacent channel leakage power ratio (ACPR). Under power control operation, the control range of the PA block increased from 23.6 dB to 31.2 db, and ACPR reduction of over 10 dB was achieved with the use of linearized VGA     

A High-Efficient CMOS RF Power Amplifier With Automatic Adaptive Bias Control

A 2.4-GHz Doherty power amplifier (PA) is developed in 0.18-mum CMOS technology. An automatic adaptive bias control circuit is integrated with the auxiliary PA to improve the overall performance of the PA. Operated at 3V, the P_{1 dB} and associated power-added-efficiency (PAE) of the PA are 21dBm and 33%, respectively. At the output power 6-dB backoff from P_{1 dB}, the PAE remains 21%. The limited PAE degradation at backoff power levels makes the PA suitable for the applications with high peak-to-average power ratio     

The Doherty Power Amplifier With On-Chip Dynamic Bias Control Circuit for Handset Application

A monolithic-microwave integrated-circuit Doherty power amplifier (PA) with an on-chip dynamic bias control circuit for cellular handset application has been designed and implemented. To improve the linearity and efficiency in the operation power ranges, the base and collector biases of the amplifiers, except the drive amplifier of the main path, are controlled according to the average output power. The base biases are controlled using the on-chip circuit and collector biases by the dc/dc chip to reduce the average dc consumption power. The power-added efficiency (PAE) is improved approximately 6% by the base dynamic bias control, and approximately 14% by the collector/base dynamic control from the class AB at Pout=16 dBm, respectively. If the dc/dc converter efficiency is 100%, the PAE could be improved approximately 17.5% from class AB, reaching to 29.2% at Pout=16 dBm. In the intermediate power level from 22 to 28 dBm, the PAE is over 34.3%. The average current consumption of the PA with the dynamic bias control is 22.5 mA in urban and 37.3 mA in suburban code-division multiple-access environments, which are reduced by 36%-46.7%, compared to the normal operation. The adjacent channel power ratio is below 47.5 dBc, and the PAE at the maximum power is approximately 43.3% in the dynamic bias operations     

Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.     

High linearity 5.2-GHz power amplifier MMIC using CPW structure technology with a linearizer circuit

A built-in linearizer was applied to improve the linearity in a 5.2-GHz power amplifier microwave monolithic integrated circuit (MMIC), which was undertaken with 0.15-μm AlGaAs/InGaAs D-mode PHEMT technology.The power amplifier (PA) was studied taking into account the linearizer circuit and the coplanar waveguide (CPW) structures. Based on these technologies, the power amplifier, which has a chip size of 1.44 × 1.10 mm~2, obtained an output power of 13.3 dBm and a power gain of 14 dB in the saturation region. An input third-order intercept point (IIP_3) of-3 dBm, an output third-order intercept point (OIP_3) of 21.1 dBm and a power added efficiency (PAE) of 22% were attained, respectively. Finally, the overall power characterization exhibited high gain and high linearity, which illustrates that the power amplifier has a compact circuit size and exhibits favorable RF characteristics. This power circuit demonstrated high RF characterization and could be used for microwave power circuit applications at 5.2 GHz.