基于GaAs pin工艺的开关滤波器组芯片

基于GaAs pin工艺,研制了频率覆盖9.9～ 14.2 GHz的三通道开关滤波器组单片微波集成电路(MMIC)芯片.开关滤波器组由输入/输出pin单刀三掷开关、带通滤波器组和pin开关偏置电路组合而成,集成在面积为4 mm×4 mm的GaAs衬底芯片上.每个支路的pin开关都采用串-并混合结构,控制电压-5 V时开关导通,+5V时开关截止.带通滤波器均采用分布参数梳状线结构,开路端加载金属-绝缘体-金属(MIM)电容减小了滤波器的尺寸.经探针台在片测试,结果表明,开关滤波器组MMIC芯片的三个通道中心插损为3.5～4.0 dB,1 dB相对带宽为16％ ～ 19％,35 dB与1 dB矩形系数比为1.9～2.2.     

一种用于嵌入式闪存的低压灵敏放大器(英文)

提出了一种适合于低电压嵌入式闪存的灵敏放大器。该灵敏放大器采用了增强电流感应的方法,使得电源电压可以降到1.5V及其以下。灵敏放大器中采用的动态位线箝位电路可以提高位线预充速度并减小功耗。本电路在0.13μm的Flash工艺中实现。测试结果表明:提出的灵敏放大器在电源电压为1.5V时,访问时间是25ns;在电源电压为1.2V时,访问时间是32ns。     

一种基于数字逻辑控制的低损耗双半桥驱动芯片

设计了一种集成双半桥和四功率开关的驱动芯片。采用双路对称设计,每一路可单独控制使能、自举和驱动。芯片内部采用高精度的基准源以及LDO电路,同时具有欠压死锁、过压保护和过温保护功能。死区控制可避免上下功率管直通大电流,自举设计可使上功率管的开启电压达到5 V,降低了功率管自身的损耗,使功率管输出达到11.90 V。采用TSMC 0.18μm BCD工艺进行流片。测试结果表明,输出的方波信号幅度为11.96 V/11.95 V,死区时间为60 ns/80 ns,静态功耗低至478μA。     

阻变存储阵列的自动化测试系统

阻变存储器(RRAM)是一种新型的不挥发存储技术,研究阻变存储器阵列规模的存储性能以及可靠性问题是推进RRAM实用化的关键.目前通用的基于微控探针台的半导体参数分析的常规测量系统无法完成对阵列的自动化测试.利用半导体参数分析仪(4200-SCS)、开关矩阵以及相关外围电路搭建了一套针对阻变存储阵列的自动测试系统,实现了1MbitRRAM芯片的初始阻态分布的读取、初始化测试、存储单元的自动化编程/擦除操作.测试结果表明,该测试系统可以实现阻变存储阵列的自动化测试,为进一步工艺参数和编程算法的优化设计奠定基础.     

基于高压大电流模块应用的3300V软穿通快速IGBT的设计

设计了3 300V/50A的软穿通型IGBT芯片(SPT IGBT),利用数值仿真软件MEDICI对其各项特性进行了仿真研究,包括静态特性、开关特性、动态雪崩特性、短路特性、电容特性和闩锁特性,在满足设计需求的同时重点进行动态失效特性仿真,验证了该器件的可靠性。仿真结果显示,器件的额定工作电流为50A、正向阻断电压为4 178.8V、阈值电压VTH为7.8V、导通压降为2.67V、短路电流为857A、工作电流为100A时的雪崩耐量为1.755J。利用局域载流子寿命控制的方法对器件进行优化后,器件的正向阻断电压仍为4 178.8V,导通压降为4.13V,没有明显的改变,关断时间由6 725.75ns降低到了1 006.49ns,关断速度提高了568%,大大提高了器件的性能,降低了损耗。     

高频PWM DC/DC转换器的设计

设计了一种基于0.6μm CMOS工艺的高频PWM升压型DC/DC转换芯片.采用恒定频率、电流模式的控制结构以提供稳定的电压.本芯片在XFAB公司流片成功,测试结果表明,芯片的开关频率高达为1.2MHz,在输入电压分别为3.3V、5V的情况下能稳定地分别驱动4个、6个白光LED,输出电压分别为12.8V、18.6V.     

基于GaAs PHEMT的5～12 GHz收发一体多功能芯片

基于GaAs赝高电子迁移率晶体管(PHEMT)工艺,研制了一种5～ 12 GHz的收发一体多功能芯片(T/R MFC),其具有噪声低、增益高和中等功率等特点.电路由低噪声放大器和多个单刀双掷(SPDT)开关构成.为了获得较低的噪声系数和较大的增益,低噪声放大器采用自偏置三级级联拓扑结构;为了获得较高的隔离度和较低的插入损耗,SPDT开关采用串并联结构.测试结果表明,在5～ 12 GHz频段内,收发一体多功能芯片的小信号增益大于26 dB,噪声系数小于4 dB,输入/输出电压驻波比小于2.0,1 dB压缩点输出功率大于15 dBm.其中,放大器为单电源5V供电,静态电流小于120 mA;开关控制电压为-5 V/0 V.芯片尺寸为2.65 mm×2.0 mm.     

一种GaN半桥驱动器电平移位电路设计

GaN半桥输出点电压在死区时间为负值,给GaN功率器件栅极驱动电路信号通信带来了挑战。通过研究驱动器电平移位锁存电路工作状态与半桥功率级输出节点电压跳变、死区时间负压之间的相互影响,设计了一种新型的零静态功耗电平移位电路及其误触发消除电路。电路采用100 V BCD 0.18μm工艺设计,在输入电压100 V、开关频率5 MHz的GaN半桥变换器中对版图进行了后仿真。仿真结果表明,当半桥功率级输出节点分别为-3 V和100 V时,延时为4.5 ns和1.5 ns。     

用于36 V、500 W GaN功率放大器的电源调制器

随着GaN功率放大器的发展,其工作电压和输出功率越来越大,对电源调制器的要求也越来越高.介绍了一种用于36 V、500 W GaN功率放大器的电源调制器模块.该模块基于自主研发的芯片组合设计而成,使用了一款50 V调制驱动器作为核心控制芯片,一款60V高压PMOSFET作为调制开关,一款固定输出电压的线性稳压器,一款负压线性稳压器为功率放大器提供栅极偏置电压.经实验验证,该模块电路可以为36 V、500 W的GaN功率放大器提供稳定可靠的漏极控制电压及栅极偏置电压.此外,栅、漏电压上电时序受控,输出信号的上升、下降时间分别为16.3 ns和79.4 ns,能够很好地满足应用要求.     

3300V碳化硅肖特基二极管及混合功率模块研制

基于数值仿真结果,采用结势垒肖特基(JBS)结构和多重场限环终端结构实现了3 300 V/50 A 4H-SiC肖特基二极管(SBD),所用4H-SiC外延材料厚度为35 μm、n型掺杂浓度为2× 1015cm-3.二极管芯片面积为49 mm2,正向电压2.2V下电流达到50 A,比导通电阻13.7 mΩ· cm2;反偏条件下器件的雪崩击穿电压为4 600 V.基于这种3 300 V/50 A 4H-SiC肖特基二极管,研制出3 300 V/600 A混合功率模块,该模块包含24只3 300 V/50 A Si IGBT与12只3 300 V/50 A 4H-SiC肖特基二极管,SiC肖特基二极管为模块的续流二极管.模块的动态测试结果为:反向恢复峰值电流为33.75 A,反向恢复电荷为0.807 μC,反向恢复时间为41 ns.与传统的Si基IGBT模块相比,该混合功率模块显著降低了器件开关过程中的能量损耗.     

A resonant switching write driver for magnetic recording

This paper describes a high-speed circuit for driving magnetic recording write heads. Resonant current switching enables a reduction in power consumption without compromising switching speed. With a 100 nH load and 120 mA_pp write currents, a rise time of 1.6 ns was achieved with a 7 V power supply     

High voltage output circuit using n- and n-LDMOSFET with thick gate oxide for PDP driver IC

A novel high voltage output circuit with thick-gated LDMOSFETs is proposed to reduce the chip size and to improve the switching speed for the plasma display panels (PDP) driver IC. The chip size of the PDP driver IC using the proposed output circuit is reduced by 35% with a similar falling time compared with the conventional one. The falling time of the proposed output circuit is about 2.5 times faster than that of the conventional one under the same size when the supply voltage and load capacitance are 180 V and 100 pF, respectively.     

An SOI-DRAM with wide operating voltage range by CMOS/SIMOXtechnology

An SOI-DRAM test device (64-Kb scale) with 100-nm-thick SOI film has been fabricated in 0.5-μm CMOS/SIMOX technology and the basic DRAM function has been successfully observed. A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. The newly introduced body-synchronized sensing scheme enhances the lower Vcc margin. The p-n junction capacitance between source/drain and a substrate for SOI structure is reduced by 25%. RAS access time tRAC is 70 ns with a 2.7-V power supply, which is as fast as the equivalent bulk-Si device with a 4-V power supply. The active current consumption is 1.1 mA (Vcc=3.0 V, 260-ns cycle) for this SOI-DRAM, which is a reduction of 65%, compared with 3.2 mA for the reference bulk-Si DRAM. The mean value of data retention time for this chip at 80°C is longer than 20 s (Vcc=3.3 V), which is the same value as mass-produced 16-Mb DRAM's. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. The observed speed enhancement and the wide operating voltage range indicate high performance at the low voltage operation suitable for battery-operated DRAM's     

一种基于多值RRAM的快速逻辑电路

针对移动物联网设备,提出一种基于多值RRAM的快速逻辑电路,以实现非易失性存储与快速逻辑运算。利用RRAM多值存储特性,采用Crossbar结构,实现了简单快速的译码器与高存储密度查找表,使逻辑电路具有较快的运算速度和较小的面积。基于该结构实现了4位、8位和16位的乘法器,其外围电路采用SMIC 65 nm CMOS工艺实现,而其核心多值RRAM则采用Verilog-A 模型模拟。仿真结果表明,与传统CMOS逻辑电路相比,基于多值RRAM的16位乘法器的速度提高了35.7%,面积减少了14%。     

Flexible rewritable organic memory devices using nitrogen-doped CNTs/PEDOT:PSS composites

Nonvolatile rewritable organic memory devices based on poly(3,4-ethylene dioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) and nitrogen doped multi-walled carbon nanotube (NCNT) nanocomposites were fabricated on glass and PET substrates.Organic memory devices with bistable resistive switching were obtained using very low NCTN concentration (∼0.002 wt%) in the polymeric matrix. The memory devices exhibited a good ON/OFF ratio of approximately three orders of magnitude, a good retention time of 10⁴ s under operating voltages ≤ |4V| and a few hundredths of write-read-erase-read cycles. The bistable resistive switching is mainly attributed to the creation of oxygen vacancies. These defects are introduced into the thin native Al oxide (AlOx) layer on the bottom electrode during the first voltage sweep. The well-dispersed NCNTs immersed in PEDOT:PSS play a key role as conductive channels for the electronic transport, hindering the electron trapping at the AlOx-polymer interface and inducing a soft dielectric breakdown of the AlOx layer. These PEDOT:PSS + NCNTs memory devices are to easy to apply in flexible low-cost technology and provide the possibility of large-scale integration.     

一种具有载流子存储层的500 V高速SOI-LIGBT

为了改善LIGBT的关断特性,已有一种采用PMOS管来控制LIGBT阳极空穴注入的方法。在此基础上,提出了一种具有载流子存储效应的高速SOI-LIGBT结构。采用二维仿真软件MEDICI,对器件P-top区的剂量、载流子存储层的长度、掺杂浓度等参数进行优化设计。结果表明,SOI-LIGBT的击穿电压为553 V,正向压降为1.73 V。关断时,引入的PMOS管可以阻止LIGBT阳极向漂移区注入空穴,使器件的关断时间下降到13 ns,相比传统结构下降了87.6%。     

An 800-MHz quadrature digital synthesizer with ECL-compatibleoutput drivers in 0.8 μm CMOS

An 800 MHz quadrature direct digital frequency synthesizer (QDDFS4) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc, The frequency resolution is 0.188 Hz with a corresponding switching speed of 5 ns and a tuning latency of 47 clock cycles. The chip is also capable of frequency and phase modulation. ECL-compatible output drivers are provided to facilitate I/O compatibility with other high speed devices. A high gain amplifier at the clock input enables the QDDFS4 chip to be clocked with ac-coupled RF signal sources with peak-to-peak voltage swings as small as 0.5 V. The 0.8 μm triple level metal N well CMOS chip has a complexity of 94000 transistors with a core area of 5.9×6.7 mm². Power dissipation is 3 W at 800 MHz and 5 V     

新型阻变存储器内的电压解决方案

相对于现在流行的FLASH型存储器,新型阻变存储器(resistive-RAM,RRAM)有很多优势,比如较高的存储密度和较快的读写速度。而针对RRAM的读写操作特性,提出了一种适用于新型阻变存储器的提供操作电压的电路。该方案解决了新型存储器需要外部提供高于电源电压的操作电压的问题,使得阻变存储器能应用于嵌入式设备。同时,对工艺波动和温度波动进行补偿,从而降低了阻变存储器的读写操作在较差的工艺和温度环境下的失败概率,具有很强的实际应用意义。该设计采用0.13μm标准CMOS 6层金属工艺在中芯国际(SMIC)流片实现,测试结果表明,采用此电路的RRAM能正确地进行数据编程和擦除等操作,测试结果达到设计要求。     

一种面向存算的高速字线驱动电路

在非易失性存算芯片(CIM)中,大规模阵列的栅极等效电容以及远距离传输导线的等效电容严重限制了字线驱动电路(WLDC)的切换速度.非易失性存算器件工作所需的多电压域的压差已远超字线驱动电路中单管耐压范围.文章提出了一种面向存算的高速字线驱动电路,结合阵列的工作原理,采取多级预处理电压控制方法,将多电压域多种高压进行可选...     

一种带有增益提高技术的高速CMOS运算放大器设计

设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构,利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度,100 MS/s采样频率的高速流水线（Pipelined）ADC的运放。设计基于SMIC 0.25μm CMOS工艺,在Cadence环境下对电路进行Spectre仿真。仿真结果表明,在2.5 V单电源电压下驱动2 pF负载时,运放的直流增益可达到124 dB,单位增益带宽720 MHz,转换速率高达885 V/μs,达到0.1%的稳定精度的建立时间只需4 ns,共模抑制比153 dB。