Measurement and modelling of high-linearity partially depleted absorber photodiode

Third-order intermodulation distortions of an InGaAs/InP partially depleted absorber photodiode (PDA-PD) using high doping levels for both p-type and n-type absorbers are characterised using a two-tone measurement technique. The third-order local intercept point (IP3) of the device increases only slightly with frequency, and remains as high as 39 dBm up to 20 GHz. The frequency characteristics of the IP3 can be well explained by an equivalent circuit model.     

A comparison of front- and backside-illuminated high-saturation power partially depleted absorber photodetectors

A systematic study of high-saturation-current p-i-n In/sub 0.53/Ga/sub 0.47/As photodiodes with a partially depleted absorber (PDA) has been made under front (p-side) and back (n-side) illumination. The photodiode structure consists of an In/sub 0.53/Ga/sub 0.47/As absorption region (450-nm p-InGaAs, 250-nm unintentionally doped InGaAs, and 60-nm n-InGaAs) sandwiched between p- and n-InP layers. For front illumination of a 34-/spl mu/m-diameter photodiode at 2-V bias the saturation currents were 23 and 24 mA at 10 and 1 GHz, respectively. Under similar conditions, backside-illumination resulted in saturation currents of 76 mA (10 GHz) and >160 mA (1 GHz). Backside illumination of a 100-/spl mu/m-diameter photodiode achieved a saturation current >400 mA. For the case of front illumination the device lateral resistance dominates whereas for backside illumination the response is determined primarily by the space charge effect.     

A unified analytical fully depleted and partially depleted SOIMOSFET model

In this paper we present a unified analytical drain current model for fully depleted and partially depleted SOI MOSFETs. The analytical model is based on a nonpinned surface potential approach and is valid in all regions of operation. It was developed by starting from a two-dimensional Poisson equation, and its accuracy has been verified with the experimental data of SOI MOSFETs     

Design and optimization of evanescently coupled waveguide photodiodes

We present the design and optimization of evanescently coupled waveguide photodiodes(EC-WPDs) based on the coupling modes theory and the beam propagation method.Efficient focalization of the optical power in the absorber is achieved by an appropriate choice of index matching layers of EC-WPDs.Numerical simulation shows that high-speed(40 GHz),high quantum efficiency(81%) and high linearity photodiodes can be achieved, and EC-WPDs are promising devices for future optical communication systems.     

Design and optimization of evanescently coupled waveguide photodiodes

We present the design and optimization of evanescently coupled waveguide photodiodes (EC-WPDs) based on the coupling modes theory and the beam propagation method. Efficient focalization of the optical power in the absorber is achieved by an appropriate choice of index matching layers of EC-WPDs. Numerical simulation shows that high-speed (40 GHz), high quantum efficiency (81%) and high linearity photodiodes can be achieved, and EC-WPDs are promising devices for future optical communication systems.     

Analysis of coaxial waveguide partially filled with chiral media

In this paper, the canonical problem of coaxial waveguide partially filled with chiral media is analyzed by a new equivalent transmission line network method. Both radial transmission lines in the cross section and multi-mode transmission lines in the longitudinal direction are introduced. The symmetrical properties of the structure are also discussed. Therefore, this method brings a clear physical picture into the wave propagation phenomena. Based on the analysis, the notable features and the role of the chirality parameter of the medium on the reflected and transmitted guided waves are discussed.     

The cryogenic operation of partially depleted silicon-on-insulatorinverters

This paper describes the cryogenic operation of inverters fabricated in a partially depleted (PD) 1 μm Silicon-on-Insulator (SOI) CMOS technology. As is shown, the floating-body effects like the kink effect degrade the static transfer characteristics considerably. Generally, the effects aggravate upon cooling. Additionally, at deep cryogenic temperatures, e.g., 4.2 K, typical low-temperature anomalies, which are related to the device freeze-out, cause hysteresis effects. Ways for improvement are discussed and compared: As is shown, the PD SOT inverter anomalies can be largely reduced by using the so-called twin-gate configuration     

Space-charge waves in partially depleted negative-mobility media

Space-charge waves in a two-dimensional negative-mobility medium are described by a relatively simple and easy-touse expression for the complex propagation constant. Attention is focused on the dominant mode in the most important limit of low growth rate. Diffusion is included in the analysis. Whereas most previous workers imposed a stiff lateral-motion constraint at the surfaces of the drifting electron stream, we allow the electrons to move freely in the transverse direction at the lateral boundaries of the stream. This free-surface assumption corresponds to the partially depleted condition which prevails in many experiments. It has the effect of reducing diffusion damping and hence enhancing the growth of space-charge waves at high frequencies. The enhanced high-frequency growth rate makes the free-surface theory agree better with experimental data on thin-layer reflection and traveling-wave amplifiers than the stiff-surface theory does. Our results are cast in a form which allows heterogeneous dielectric media to be characterized by a single "effective dielectric constant." Dielectric configurations considered include symmetrical and unsymmetrical combinations of simple dielectric media, multilayered dielectric media, and simple or multilayered dielectric media with metal backing.     

Light dependence of partially depleted SOI-MOSFET's using SIMOXsubstrates

The optical dependence of partially depleted MOSFET's on SIMOX substrates is investigated. Measurements of the electrical and optical characteristics are presented. In order to make use of the threshold voltage shift due to optical generation of carriers in the film a comparator circuit was realized, which can be switched by a light pulse. Possible applications can be found in the optically coupled signal transmission in the lower frequency range for intelligent power devices     

Noise analysis methodology for partially depleted SOI circuits

In partially depleted silicon-on-insulator (PD-SOI) technology, signal switching history and intial state of the circuit nodes can affect the device body voltage and also cause parasitic BJT leakage currents, which can lead to significant increase in noise propagation and noise failures. In this brief we explore the effects of input switching history, initial circuit conditions and the parasitic BJT device on all steps in a traditional noise analysis methodology: noise injection, noise propagation, and noise failure criterion. We present a new noise analysis methodology to account for the floating body and the BJT effects in PD SOI technology. We demonstrate the new technique on an industrial microprocessor design in PD SOI and show that the current noise analysis methods do not account for 56% of noise fails.     

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for     

Performance enhancement of partially and fully depleted strained-SOI MOSFETs

The authors have developed short-channel strained-silicon-on-insulator (strained-SOI) MOSFETs on silicon-germanium (SiGe)-on-insulator (SGOI) substrates fabricated by the Ge condensation technique. 35-nm-gate-length strained-SOI MOSFETs were successfully fabricated. The strain in Si channel is still maintained for the gate length of 35 nm. The performance enhancement of over 15% was obtained in 70-nm-gate-length strained-SOI n-MOSFETs. Fully depleted strained-SOI MOSFETs with back gate were successfully fabricated on SGOI substrate with SiGe layers as thin as 25 nm. The back-gate bias control successfully operated and the higher current drive was obtained by a combination of the low doping channel and the back-gate control.     

EOS/ESD reliability of partially depleted SOI technology

A model for predicting the electrostatic discharge (ESD) protection level of PD-SOI MOSFETs and diodes is presented along with data to support the model. The form of the model is compatible with circuit simulators. An important design rule for layout of multifinger SOI ESD protection MOSFETs has been derived from the model. We present experimental data to support this design rule     

Principles of transient charge pumping on partially depleted SOIMOSFETs

A new method to determine the interface trap density in partially depleted silicon-on-insulator (SOI) floating body MOSFETs is proposed for the first time. It can be considered as a "transient" charge-pumping (CP) technique in contrast to the normally used "steady-state" method. In our technique, majority carriers are removed from the floating body by applying a burst of pulses to the transistor gate. The change in the linear drain current after each pulse is used to determine the device interface trap density. The unique advantage of this method is the possibility to use it to characterize SOI MOSFETs without a body contact. The technique proposed is simple, reliable, and can be used for the characterization of deep submicron devices     

On the transient operation of partially depleted SOI NMOSFET's

The transient operation of partially depleted (PD) Silicon-On-Insulator (SOI) NMOSFET's is investigated, based on two-dimensional numerical simulations. The studied devices have a gate length of 0.2 μm and a floating body. They are designed for a supply voltage of 2 V. In the case of gate transient, we show that the body voltage is more influenced by the capacitive coupling with the gate electrode than the impact ionization current. Further, we demonstrate, for the first time, that the anomalous subthreshold slope, that exists in a DC static transfer I-V curve, does not exist in fast transient mode because the minimum time constant for body charging by impact ionization current is on the order of 3 ns in such devices     

Hysteresis effect in pass-transistor-based, partially depleted SOICMOS circuits

This paper presents a detailed study on the hysteretic delay variations of pass-transistor-based circuits with floating-body partially depleted silicon-on-insulator CMOS devices. It is shown that the pass-transistor can be conditioned into a initial state with extremely high body voltage (exceeding the power supply voltage V_DD ), thus resulting in highly hysteretic delay variations when the body subsequently loses charges through the switching cycles. Basic physical mechanisms underlying the hysteretic circuit behavior and its frequency dependence are examined. Different initial states of the circuit are shown to cause large delay disparity at the beginning of the switching activity, yet they converge as the circuit approaches steady state. Use of a cross coupled dual-rail circuit configuration is shown to be very effective in reducing the hysteretic delay variation and its frequency dependence     

The low-frequency noise overshoot in partially depleted n-channelsilicon-on-insulator twin-MOST's

This paper investigates the effect of the so-called twin-MOST structure on the kink-related low-frequency (LF) noise overshoot, which is observed in partially depleted (PD) SOI nMOST's. It is demonstrated that a significant reduction of the noise overshoot amplitude may be achieved in such a configuration, compared with a single transistor having the same effective gate length. The observed reduction is stronger than the one predicted on purely geometrical grounds, indicating that the floating body effects are indeed successfully reduced by this structure     

Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

Partially depleted silicon-on-insulator (PD-SOI) technology has garnered more attention recently with regards to replacing traditional bulk-silicon technology as the mainstream technology of choice for high-performance/low-power digital applications. The increase in performance is due to the buried oxide layer, which provides a dramatic decrease in the source and drain junction capacitance, as well as a reduction in the traditional back biasing resulting from the body effect. The reported performance increases have been between 20% and 35%. However, this increase in performance comes at a cost of complexity from a performance measurement and delay testing perspective. Where the SOI transistor is faster than the bulk transistor, there exists a variation in delay caused by threshold voltage shifts that must be accounted for during manufacturing test. This paper explores these issues and proposes new test techniques for this promising technology.     

Erbium-ytterbium waveguide laser mode-locked with a semiconductorsaturable absorber mirror

Picosecond pulses are produced using a semiconductor saturable absorber mirror in a laser based on an Er-Yb codoped planar waveguide amplifier. Continuous-wave mode-locking (CWML) with 9.8-ps pulses is obtained at repetition rates up to 100 MHz. With intracavity spectral filtering, saturable pulsewidths of 1 ps are achieved, and tunable picosecond pulses are obtained from 1534 to 1553 nm. Absorber characterization suggests that two-photon absorption within the saturable absorber mirror influences the CWML stability     

A partially metal-clad-dielectric-slab waveguide for integrated optics

Characteristics of a partially metal-clad-dielectric-slab waveguide are described. In this waveguide a propagating field is confined two-dimensionally by the difference of effective indices of refraction between a dielectric-clad region and a metal-clad region. Experimental results are also described.