Electrical characterization and quantum modeling of MOS capacitors with ultra-thin oxides (1.4–3 nm)

Electrical characterization of MOS capacitors with ultra-thin oxides (1.4–3 nm) has been carried out. The validity of the correction to C–V data, needed to take into account the series resistance and leakage current, is discussed. The gate current in accumulation and in depletion regions has been investigated and properly modeled based on detailed analysis of tunneling from the polygate.     

A function-fit model for the hard breakdown I–V characteristics of ultra-thin oxides in MOS structures

A function-fit model for the hard breakdown current–voltage characteristics of ultra-thin oxides in metal–oxide–semiconductor structures based on the smoothing function concept is presented. The model is intended to capture the diode-like and resistance-like behaviours observed at low and high applied biases, respectively, by means of a simple, continuous and derivable function. These features make the proposed expression suited for circuit simulation environments. The effect of temperature on the model parameters is also analysed.     

Prediction of dielectric reliability from I–V characteristics: Poole–Frenkel conduction mechanism leading to √E model for silicon nitride MIM capacitor

Two assumptions lead to a correlation between the leakage mechanism of a dielectric and dielectric reliability: the degradation of the dielectric is a direct cause of the leakage current flowing through the dielectric and breakdown occurs after a critical charge has been forced through the dielectric. The field and temperature dependence of the leakage current mechanism then determine the voltage acceleration factor and the activation energy of TDDB experiments. This simple physical model describes the reliability of metal insulator metal (MIM) capacitors with PECVD SiN remarkably well. The current conduction mechanism is described by Poole–Frenkel theory, leading to a √E dependence of the time to breakdown on the applied electric field. The model predicts correctly the voltage acceleration factor and its temperature dependence and the activation energy.     

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (<2.0 nm) single layer and dual layer gate oxides

Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.