Thermal Ta2O5––alternative to SiO2 for storage capacitor application

Tantalum pentoxide thin layers (10–100 nm) obtained by thermal oxidation of rf sputtered Ta films on Si have been investigated with respect of their dielectric, structural and electric properties. It is established that stoichiometric Ta₂O₅ detected at the surface of the layers is reduced to tantalum suboxides in their depth. The oxide parameters are discussed in terms of a presence of an unavoidable ultrathin SiO₂ between Si and Ta₂O₅ and bond defects in both the oxide and the interface transition region. Conditions which guarantee obtaining high quality tantalum oxide with a dielectric constant of 32–35 and a leakage current less than 10⁻⁷–10⁻⁸ A/cm² at 1.5 V (SiO₂ equivalent thickness of 2.5–3 nm) are established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAMs application.     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

Hafnium oxide thin films deposited by high pressure reactive sputtering in atmosphere formed with different Ar/O2 ratios

The physical and electrical properties of hafnium oxide (HfO₂) thin films deposited by high pressure reactive sputtering (HPRS) have been studied as a function of the Ar/O₂ ratio in the sputtering gas mixture. Transmission electron microscopy shows that the HfO₂ films are polycrystalline, except the films deposited in pure Ar, which are amorphous. According to heavy ion elastic recoil detection analysis, the films deposited without using O₂ are stoichiometric, which means that the composition of the HfO₂ target is conserved in the deposition films. The use of O₂ for reactive sputtering results in slightly oxygen-rich films. Metal-Oxide-Semiconductor (MOS) devices were fabricated to determine the deposited HfO₂ dielectric constant and the trap density at the HfO₂/Si interface (D_it) using the high–low frequency capacitance method. Poor capacitance–voltage (CV) characteristics and high values of D_it are observed in the polycrystalline HfO₂ films. However, a great improvement of the electrical properties was observed in the amorphous HfO₂ films, showing dielectric constant values close to 17 and a minimum D_it of 2×10¹¹ eV⁻¹ cm⁻².     

Influence of oxidation temperature on the microstructure and electrical properties of Ta2O5 on Si

The effect of the oxidation temperature (673-873 K) on the microstructural and electrical properties of thermal Ta₂O₅ thin films on Si has been studied. Auger electron spectroscopy and X-ray photoelectron spectroscopy results revealed that the films are non-stoichiometric in the depth; an interfacial transition layer between tantalum oxide and Si substrate, containing presumably SiO₂ was detected. It has been found by X-ray diffraction that the amorphous state of Ta₂O₅ depends on both the oxidation temperature and the thickness of the films—the combination of high oxidation temperature (>823 K) and thickness smaller than 50 nm is critical for the appearance of a crystal phase. The Ta₂O₅ layers crystallize to the monoclinic phase and the temperature of the phase transition is between 773 and 823 K for the thinner layers (<50 nm) and very close to 873 K for the thicker ones. The electrical characterization (current/voltage; capacitance/voltage) reveals that the optimal oxidation temperature for achieving the highest dielectric constant (∼32) and the lowest leakage current (10⁻⁸ A/cm² at 1 MV/cm applied field) is 873 K. The results imply that the poor oxidation related defects are rather the dominant factor in the leakage current than the crystallization effects.     

Correlation between infrared transmission spectra and the interface trap density of SiO2 films

This work is an attempt to estimate the electrical properties of SiO₂ thin films by recording and analyzing their infrared transmission spectra. In order to study a big variety of films having different infrared and electrical properties, we studied SiO₂ films prepared by low pressure chemical vapor deposition (LPCVD) from SiH₄ + O₂ mixtures at 425 °C and annealed at 750 °C and 950 °C for 30 min. In addition thermally grown gate quality SiO₂ films of similar thickness were studied in order to compare their infrared and electrical properties with the LPCVD oxides. It was found that all studied SiO₂ films have two groups of Si–O–Si bridges. The first group corresponds to bridges located in the bulk of the film and far away from the interfaces, the grain boundaries and defects and the second group corresponds to all other bridges located near the interfaces, the grain boundaries and defects. The relative population of the bulk over the boundary bridges was found equal to 0.60 for the LPCVD film after deposition and increased to 4.0 for the LPCVD films after annealing at 950 °C. Thermally grown SiO₂ films at 950 °C were found to have a relative population of Si–O–Si bridges equal to 3.9. The interface trap density of the LPCVD film after deposition was found equal to 5.47 × 10¹² eV⁻¹ cm⁻² and decreases to 6.50 × 10¹⁰ eV⁻¹ cm⁻² after annealing at 950 °C for 30 min. The interface trap density of the thermally grown film was found equal to 1.27 × 10¹¹ eV⁻¹ cm⁻² showing that films with similar Si–O–Si bridge populations calculated from the FTIR analysis have similar interface trap densities.     

Effect of microwave radiation on the properties of Ta2O5–Si microstructures

The paper presents results of the effect of microwave irradiation at room temperature on the properties of thin layers of tantalum pentoxide deposited on Si by rf sputtering. Electrical characterization is performed in conjunction with Auger electron spectroscopy and atomic force microscopy. Among exposure times used (1; 5; 10 s), treatment of about 5 s shows the best promise as an annealing step––an improvement of number of parameters of the system Ta₂O₅–Si is established (dielectric constant and surface morphology; stoichiometry and microstructure of both the bulk oxide and the interfacial transition region; electrical characteristics in terms of oxide charge density, leakage current and breakdown fields). At the same time the microwave irradiation is not accompanied by crystalization effects in Ta₂O₅ and/or additional oxidation of Si substrate. It is concluded that the short-time microwave irradiation can be used as an annealing process for Ta₂O₅–Si microstructures and it has a potential to replace the high-temperature annealing processes for high-k insulators.     

Towards metal electrode interface scavenging of rare-earth scandates: A Sc2O3 and Gd2O3 study

Amorphous Gd₂O₃ and Sc₂O₃ thin films were deposited on Si by high-pressure sputtering (HPS). In order to reduce the uncontrolled interfacial SiO_x growth, firstly a metallic film of Gd or Sc was sputtered in pure Ar plasma. Subsequently, they were in situ plasma oxidized in an Ar/O₂ atmosphere. For post-processing interfacial SiO_x thickness reduction, three different top metal electrodes were studied: platinum, aluminum and titanium. For both dielectrics, it was found that Pt did not react with the films, while Al reacted with them forming an aluminate-like interface and, finally, Ti was effective in scavenging the SiO₂ interface thickness without severely compromising gate dielectric leakage.     

Structural and electrical properties of radio frequency magnetron sputtered tantalum oxide films: Influence of post-deposition annealing

The as-deposited and annealed radio frequency reactive magnetron sputtered tantalum oxide (Ta₂O₅) films were characterized by studying the chemical binding configuration, structural and electrical properties. X-ray photoelectron spectroscopy and X-ray diffraction analysis of the films elucidate that the film annealed at 673 K was stoichiometric with orthorhombic β-phase Ta₂O₅. The dielectric constant values of the tantalum oxide capacitors with the sandwich structure of Al/Ta₂O₅/Si were in the range from 14 to 26 depending on the post-deposition annealing temperature. The leakage current density was <20 nA cm^?2 at the gate bias voltage of 0.04 MV/cm for the annealed films. The electrical conduction mechanism observed in the films was Poole–Frenkel.     

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors

The HfO₂ high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO₂ thin films with 9.45 nm thickness have been used for Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current-voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10¹⁰, 9.25 × 10¹¹ cm⁻² eV⁻¹ and 9.12 × 10⁻⁶ A/cm² respectively for annealed HfO₂ thin films.     

Effect of O+ implantation on silicon-silicon dioxide interface properties

A detailed investigation has been made by the MOS capacitance method, into the mechanism by which the fixed positive surface state charge, due to silicon rich oxide near SiSiO₂ interface, is controlled by O⁺ implantation into the oxide near the SiSiO₂ interface, and subsequent heat treatment. High dosage implantation of 3 × 10¹³ O⁺ ions cm^?2 results in damage in oxide which is occured by 450°C annealing. However, low dosage implantation of 3 × 10^?2 produces no detectable damage in the oxide, and increases the effective positive charge in the oxide at Si'SiO₂ interface. It is shown that prolonged 450°C heat treatment of 0⁺ ion implanted oxides results in an oxygen-silicon reaction in the silicon enriched oxide layer and reduces the fixed positive surface state charge. Subsequent heat treatments at 838°C increase the positive surface state charge to the original pre-ion implantation values, hence converting the oxide into the original silicon rich condition.     

A new MOD method to prepare Sr0.7Bi2.2Ta2O9 ferroelectric films for non-volatile RAM memories

Strontium bismuth tantalate, Sr_0.7Bi_2.2Ta₂O₉ (SBT), thin films were prepared by a new metalorganic decomposition (MOD) method using strontium (2,2,6,6-tetramethyl-3,5-heptanedionate), bismuth (2,2,6,6-tetramethyl-3,5-heptanedionate), and tantalum ethoxide as the metalorganic precursors. Films with a thickness of 300 nm were prepared on Si(1 0 0) with a layered bottom electrode (Pt/TiO₂/SiO₂). After crystallization in oxygen for 60 min at 750°C, single orthorhombic-phased films were obtained as determined by XRD, but no preferred crystalline orientation was revealed using this technique. Characterization by AFM showed that the polycrystalline films were densely packed and crack-free, and had an average surface roughness (rms) of 8 nm and a mean grain size of 150 nm. The remnant polarization and coercive field were 6 μC cm⁻² and 74 kV cm⁻¹, respectively. The SBT films showed a very low polarization fatigue after 10¹¹ switching cycles and good retention properties.     

Breakdown fields and conduction mechanisms in thin Ta2O5 layers on Si for high density DRAMs

The conduction mechanisms and the microstructure of rf sputtered Ta₂O₅ on Si, before and after oxygen annealing at high temperatures (873, 1123 K; 30 min) have been investigated. The as-deposited and annealed at 873 K layers are amorphous whereas crystalline Ta₂O₅ (orthorhombic β-Ta₂O₅ phase) was obtained after O₂ treatment at 1123 K. The results (electrical, X-ray diffraction, transmission electron microscopy) reveal the formation of an interfacial ultrathin SiO₂ layer under all technological regimes used. The higher (493 K) substrate temperature during deposition stimulates the formation of amorphous rather than crystalline SiO₂. It is found that the oxygen heating significantly reduces the oxide charge (Q_f<10¹⁰ cm⁻²) and improves the breakdown characteristics (the effect is more pronounced for the higher annealing temperature). It is accompanied by an increase of the effective dielectric constant (up to 37 after 1123 K treatment). It is established that the influence of the oxygen treatment on the leakage current is different depending on the film thickness, namely: a beneficial effect for the thinner and a deterioration of leakage characteristics for thicker (80 nm) films. A leakage current density as low as 10⁻⁷ A/cm² at 1 MV/cm applied field for 26 nm annealed layers has been obtained. The current reduction is considered to be due to a removal by annealing of certain structural nonperfections present in the initial layers. Generally, the results are discussed in terms of simultaneous action of two opposite and competing processes taking place at high temperatures––a real annealing of defects and an appearance of a crystal phase and/or a neutral traps generation. The contribution of the neutral traps also is involved to explain the observed weaker charge trapping in the as-fabricated films compared to the annealed ones.The conduction mechanism of the as-deposited films is found to be of Poole–Frenkel (PF) type for a wide range of applied fields. A change of the conduction mechanism for the annealed films at medium fields (0.8–1.3 MV/cm) is established. This transition from PF process to the Schottky emission limited current is explained with an annealing of bulk traps (oxygen vacancies and nonperfect bonds). It is concluded that the dominant conduction mechanism in the intermediate fields can be effectively controlled by appropriate technological steps.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Electroluminescence from Au/Si/SiO2/p-Si structure

Si/SiO₂ films have been grown using the two-target alternation magnetron sputtering technique. The thickness of the SiO₂ layer in all the films was 8 nm and that of the Si layer in five types of the films ranged from 4 to 20 nm in steps of 4 nm. Visible electroluminescence (EL) has been observed from the Au/Si/SiO₂/p-Si structures at a forward bias of 5 V or larger. A broad band with one peak 650–660 nm appears in all the EL spectra of the structures. The effects of the thickness of the Si layer in the Si/SiO₂ films and of input electrical power on the EL spectra are studied systematically.     

Full-band tunneling in high-κ dielectric MOS structures

High-κ oxides such as ZrO₂ and HfO₂ have attracted great interest, due to their physical properties, suitable to replacement of SiO₂ as gate dielectric materials. In this work, we investigate the tunneling properties of ZrO₂ and HfO₂ high-κ oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab initio band dispersions. Transmission coefficients and tunneling current have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with equivalent oxide thickness.     

Transport process in thin SiO2 films with an embedded 2-D array of Si nanocrystals

This work deals with the electrical characteristics and physical properties of novel dielectric systems based on silicon nanocrystals embedded in SiO₂ matrices. In particular, the transport phenomena of 10 nm thick SiO₂ capacitors with an embedded thin layer (5 nm) of LPCVD Si nanocrystals, located at different tunneling distances from the oxide–substrate interface, are studied. An original model based on an elastic tunneling phenomenon, which allows an efficient evaluation of the main structural characteristics of Si dots, is proposed.     

Carrier mobility in inversion layers of Si–thin Ta2O5 structures

The behaviour of carrier mobility in the inversion channel of gateless p-MOSFETs with thin (7-50 nm) Ta₂O₅ layers, having a dielectric constant of (23-27) and prepared by rf sputtering of Ta in an Ar-O₂ mixture, has been investigated. It is shown that independently of the high dielectric constant of the layers, the transport properties in the channel are strongly affected by defects in Ta₂O₅/Si system in the form of oxide charge and interface states. These defects act as scattering centers and are responsible for the observed minority carrier mobility degradation. Both, the oxide and the interface state charges are virtually independent on the oxygen content (in the range 10-30%) during the sputtering process. A reduction of the oxide charge and the density of interface states with increasing Ta₂O₅ film thickness was found, which results in the observed increase of the inversion channel mobility with thickness. It is assumed that the bond defects (broken or strained Ta-bonds as well as weak Si-O bonds in the transition region between Ta₂O₅ and Si) are much more probable sources of defect centers rather than Ta and O vacancies or impurities.     

Praseodymium based high-k dielectrics grown on Si and SiC substrates

High-k polycrystalline Pr₂O₃ thin films have been deposited by metal organic chemical vapor deposition (MOCVD) technique on Si(0 0 1) and 4H–SiC(0 0 0 1) substrates. MOCVD processes have been carried out from the Pr(tmhd)₃ (H-tmhd= 2,2,6,6-tetramethyl-3,5-heptandione) precursor. Complete structural and morphological characterization of films has been carried out using several techniques (X-ray diffraction (XRD), scanning electron microscopy (SEM), transmission electron microscopy (TEM)). Polycrystalline Pr₂O₃ films have been obtained and at the interface a praseodymium silicate amorphous layer has been observed on both substrates. The electrical properties of the dielectric praseodymium films have been evaluated.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.