Oxide reliability of drain engineered I/O NMOS from hot carrier injection

The impact of hot carrier stress on the breakdown properties of I/O NMOS gate oxide is reported. I/O NMOS devices with drain structures using standard LDD with pocket (S-LDD) and graded LDD without pocket (G-LDD) are used. Time-dependent (TDDB) and voltage-ramp (VRDB) dielectric breakdown tests are performed for devices with and without hot-carrier-injection. It is demonstrated that both I/O structures show similar oxide integrity after hot carrier injection (HCI) when the Idsat degradation is small (<5%), but show significantly different oxide lifetimes when the Idsat degradation is high (>5%). At 10% I/sub dsat/ degradation, the oxide lifetime for the G-LDD structure is reduced by about a factor of 10 compared to that of the S-LDD structure. The correlation between oxide integrity and leakage current indicates that the oxide charge introduced by HCI stress is the reason for oxide degradation. This work clearly demonstrates that the effect of hot carrier induced oxide damage must be included when predicting the oxide lifetimes of advanced I/O NMOS devices.     

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Since hot carrier effects can pose a potential limit to device scaling, hot-carrier-induced device degradation has been one of the major concerns in modern device technology. Currently, there is a great interest in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation. Also, low-temperature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS devices. Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degradation were done at room temperature and little has been done at low temperature. In this work, hot-carrier-induced device degradation is characterized from 77 K to room temperature for both NMOS and PMOS devices with the emphasis on low-temperature behavior of hot carrier degradation. For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature. It is also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature. For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Hot carrier stressing on PMOS devices at low temperature appears to induce hole generation and substantial interface state creation upon annealing unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures     

Clustering of plasma nitridation and post anneal steps to improve threshold voltage repeatability

The incorporation of nitrogen into gate dielectrics produces a shift in the threshold voltage, V/sub t/, and its concentration must be precisely controlled to maintain the V/sub t/ within a specified range. The V/sub t/ sensitivity to nitrogen concentration is presented to define control limits for its incorporation. The nitrogen loss as a function of time between processing steps is determined to assess the risk in a manufacturing environment. A typical foundry fab is then modeled to determine the range and distribution of possible delay times and its impact on lot to lot variation in V/sub t/. This variability can then be removed by clustering the nitridation and post anneal steps.     

Improvement of hot carrier reliability with deuterium anneals formanufacturing multilevel metal/dielectric MOS systems

This paper discusses new experimental findings critical for process integration of deuterium post-metal anneals to improve channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Detailed account of the deuterium process optimization experiments varying temperature, time, and ambient is given. Specifically, the first demonstration of the large hydrogen/deuterium isotope effect for multilevel metal/dielectric MOS systems is reported. Previous accounts of the isotope effect had been limited to CMOS structures with one-level of dielectric/metal and to about a 10 fold improvement in reliability. Deuterium, instead of hydrogen is introduced via an optimized post-metal anneal process to achieve a 50-100 fold improvement in transistor channel hot carrier lifetime. The benefits of the deuterium anneal are still observed even if the post-metal anneal is followed by the final SiN cap wafer passivation process. It is concluded that the deuterium post-metal anneal process is suitable for manufacturing high performance CMOS products and fully compatible with traditional integrated circuit processes     

A comparison of hydrogen and deuterium plasma treatment effects onpolysilicon TFT performance and dc reliability

We compare the performance and dc reliability of conventional top-gate, self-aligned polysilicon (poly-Si) thin-film transistors (TFT's) after passivation by plasma deuteration and conventional plasma hydrogenation. An optimum deuteration temperature of 300°C is found, as compared to 350°C for hydrogenation. Deuteration yields comparable TFT performance as hydrogenation, while deuterated TFT's exhibit increased resistance to threshold voltage degradation under dc stress. These results indicate that deuteration is a promising alternative to hydrogenation for achieving high-performance, high-reliability poly-Si TFT's for applications such as flat-panel displays     

Building in reliability with latch-up, ESD and hot carrier effects on 0.25 μm CMOS technology

In this study, three major reliability aspects, hot carrier effects, latch-up and electrostatic discharge (ESD) have been simultaneously studied on a 0.25 μm complementary metal-oxide silicon (CMOS) technology. For this purpose, three source–drain architectures large angle tilted implementation drain (LATID, MDD, Abrupt) processed on different kinds of substrate (bulk and epitaxial ones) are compared with respect to these three reliability aspects. This work clearly demonstrates the dependence existing between them. The source–drain architecture affects, of course, the hot carrier reliability but also the ESD performances. A thinner epitaxial substrate is effective in reducing latch-up occurrences, but degrades the ESD failure threshold. Consequently, global technology optimisation will be a trade off between these various reliability aspects.     

Effects of measurement frequency and temperature anneal on differential gate capacitance spectra observed in hot carrier stressed MOSFET's

Hot carrier generated fixed and interface traps, located at the Si-SiO/sub 2/ interface near the drain junction, are observed from the gate-to-drain capacitance of the MOS transistor, using an AC measurement signal applied to the drain. When the channel is biased in inversion, the drain junction is forward biased and carriers from the AC signal source are readily injected into the channel, leading to charge exchange between the inversion carriers and the traps located in one half of the band gap. In channel depletion, the drain junction is reverse biased, and charge exchange is between the substrate majority carriers and traps located in the other half of the band gap. The charge interaction manifests itself in a differential gate capacitance, extracted from pre- and post-stress gate capacitance voltage curves. The differential capacitance spectrum shows two distinct peaks, which are attributed to the response of donor and acceptor interface traps, located on either half of the band gap. This model is supported by capacitance measurements at different frequencies. Lower frequencies lead to a proportionally larger increase in the depletion regime response. Prolonged stress results in the convolution of the two peaks. A reverse bias on the drain leads to the deconvolution of the spectrum, allowing the two peaks to be clearly resolved. Trap response may be masked by the fixed charge, but this can be overcome by depopulation of trapped electrons or neutralization of trapped holes through elevated temperature anneal. The differential gate-to-drain capacitance allows the electrical identification of both donor and acceptor interface traps in the same device.<>     

Observations on the recovery of hot carrier degradation of hydrogen/deuterium passivated nMOSFETs

Degradation due to hot-carrier injection and the recovery due to annealing in air have been investigated in long channel nMOSFETs, where the passivation of the dangling bonds at the Si/SiO₂ interface in the post metal anneal step is done with hydrogen or deuterium. The devices with deuterium passivation exhibit less degradation than the devices with hydrogen due to the well-known isotope effect. However, the recovery of hot-carrier induced degradation by thermal annealing in air is found to be independent of the isotope. An Arrhenius activation energy (E_a) of around 0.18 eV for threshold voltage (V_T) recovery for both types of devices was calculated, indicating that the recovery mechanism may be the same.     

Assessment of oxide reliability and hot carrier degradation in CMOS technology

The techniques and methodologies to be applied in R&D laboratories for the assessment of thin gate dielectrics reliability and hot carrier degradation are reviewed. Examples are given on how the application of these techniques allows to obtain a better insight in the physics of the degradation process. Two such examples are given related to the Dielectric breakdown of thin gate dielectrics and on the Stress-Induced Leakage Current in thin dielectrics.     

Voltage stress-induced hot carrier effects on SiGe HBT VCO

This paper presents the hot carrier (HC) induced performance degradation in a 10 GHz voltage controlled oscillator (VCO) with SiGe heterojunction bipolar transistors (HBTs). SiGe device characteristics due to HC stress are examined experimentally. The vertical bipolar inter-company (VBIC) model parameters extracted from measured data are used in Cadence SpectreRF simulation to verify the HC effect on the VCO. The VCO shows significant vulnerability to hot carriers.     

The effects of thermal nitridation conditions on the reliability of thin nitrided oxide films

MIS capacitors on n-type silicon substrate with thin oxide films thermally nitrided in NH3gas ambient at different temperatures and for different times have been fabricated. The effects of nitridation temperature and time on the properties of the thin nitrided oxide films have been examined and analyzed by using a constant current stress. It is found that the oxide films nitrided at 900°C exhibit much improved total charge to breakdown and interface trap generation if proper nitridation time is used. The superior characteristics of the fabricated nitrided oxide films using the proposed optimum conditions are suitable for existing CMOS/VLSI applications.     

Theory of hot carrier effects on nonlinear gain in GaAs-GaAlAslasers and amplifiers

A concise and straightforward model of nonlinear grain based on the carrier heating effect in semiconductor lasers is presented. The problem is formulated using the density matrix approach and includes a priori the effect of free-carrier absorption. Coupled field-medium equations involving photon densities, carrier densities, and carrier temperatures are derived using the results of the density matrix method. The propagation of ultrashort pulses in laser amplifiers is studied and a qualitatively new model along with results on the transient gain recovery dynamics are presented. The model accounts for the wavelength dependence of the asymmetric part of the nonlinear gain observed in direct mixing experiments observed in semiconductor lasers     

Impact of the interaction between nitrogen implant and NO anneal on narrow-width transistors

This study reports a new behavior in narrow-width transistors resulting from the interaction of oxides grown with nitrogen implant with the nitridation associated with growing other oxides. Nitric oxide (NO) annealing of 28-/spl Aring/ oxides grown on nitrogen-implanted silicon results in the decrease of NMOS threshold voltage and in the increase (absolute value) of PMOS threshold with decreasing width. This effect arises from the positive charge from NO anneal interacting with the parasitic transistor associated with the shallow trench isolation edge recess. The parasitic impact becomes more pronounced for narrower widths due to higher effect of recess on total transistor width.     

Inelastic scattering effects on carrier relaxation in quantum well-based hot electron structures

We calculate the inelastic scattering rate of “hot” electrons injected into doped quantum well structures by including on an equal footing, both the electron-electron (Coulomb) and the electron-polar optical phonon (Fröhlich) interaction effects in the theory within the dynamical random-phase-approximation. Our theory includes in a consistent diagrammatic approximation effects of quantum statistics, dynamical screening and phonon renormalization (i.e. the so-called “plasmon-phonon coupling” effect). Our results, obtained for the two-dimensional, the quasi-two-dimensional and the three-dimensional models, are appropriate for a number of transport and optical experiments including ballistic hot-electron transport, resonant tunneling, femtosecond carrier relaxation, and, planar parallel transport.     

A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration

A systematic investigation of the influences of high substrate doping on the hot carrier characteristics of small geometry n-MOSFETs down to 0.1 /spl mu/m has been carried out. Results indicate that the dependence of substrate current and impact ionization rate on substrate impurity concentration is reversed in long channel and short channel devices. In the long channel case, both increase with rising substrate impurity concentration, while they decrease in the case of short channel devices. An explanation for this phenomenon based on the lucky electron model has been developed. The dependence of other characteristics on impurity concentration has also been studied. The dependence of off-leakage current has been found to fall as the gate oxide is reduced in thickness. Regarding the dependence of hot carrier degradations, the degradation of drain currents becomes smaller as the substrate impurity concentration increases in the case of short channel devices. Further, in the extremely high impurity doping region, a new hot carrier degradation mode was found, in which the maximum transconductance values of n-MOSFETs increase after hot carrier stress. This new degradation mode can be explained in terms of effective channel length shortening caused by electron trapping.<>     

Effects of the post nitridation anneal temperature on performances of the nano MOSFET with ultra-thin (<2.5 nm) plasma nitrided gate dielectric

A post nitridation annealing (PNA) is used to improve performances of the metal oxide semiconductor field effect transistor (MOSFETs) with nano scale channel and pulsed radio frequency decoupled plasma nitrided ultra-thin (<50 Å) gate dielectric. Effects of the PNA temperature on the gate leakage and the device performances are investigated in details. For a n-type MOSFET, as the PNA temperature rises from 1000 to 1050 °C, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements in performance are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. Most of all, the high temperature PNA does not degrade the gate oxide integrity.     

Noise and hot carrier effects in a single injection solid state diode

In an earlier paper, analytical expressions for the scattering noise in single injection diodes operating far in the hot carrier regime were derived. In this paper the scattering noise is numerically calculated for the whole range of applied voltages of interest and, in addition, an extrinsic semiconductor is considered as starting material. The results are presented in two figures.     

New experimental findings on hot carrier effects in deep submicrometer surface channel PMOS

The correlation between gate current and substrate current in surface channel(SC) PMOS with effective channel length down to 0.15 μm is investigated within the general framework of the lucky-electron model. It is found that the impact ionization rate increases, but the device degradation is not serious in deep submicrometer PMOS. To extend the lucky-electron model to deep submicrometer regime, we empirically model the effective pinch-off length as a function of the gate length and the gate bias voltage. SCIHE is suggested as the possible physical mechanism for the enhanced impact ionization and the gate current reduction.     

New experimental findings on hot carrier effects in sub-0.1 μmMOSFET's

The behaviors of the substrate current and the impact ionization rate are investigated for deep submicron devices in a wide temperature range. New important features are shown for the variations of the maximum substrate current as a function of applied biases and temperature. It is found that the gate voltage V_gmax, corresponding to the maximum impact ionization current conditions, is quasi-constant as a Function of the drain bias for sub-0.1 μm MOSFET's in the room temperature range. At low temperature, a substantial increase of V_gmax is observed when the drain voltage is reduced. It is also shown that, although a significant enhancement of hot carrier effects is observed by scaling down the devices, a strong reduction of the impact ionization rate is obtained for sub-0.1 μm MOSFET's operated at liquid nitrogen temperature in the low drain voltage range