Reduction of source/drain series resistance and its impact ondevice performance for PMOS transistors with raised Si1-xGex source/drain

P-channel MOS transistors with raised Si_1-xGe_x and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si_1-xGe_x and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si_1-xGe_x S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R_SD), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R_SD of devices with Si_1-xGe_x raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g_m) at an effective channel length of 0.16 μm. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si_1-xGe_x S/D structure very attractive for future sub-0.1 μm p-channel MOS transistors     

Strained n-Channel Transistors With Silicon Source and Drain Regions and Embedded Silicon/Germanium as Strain-Transfer Structure

We report the demonstration of 55 nm gate length strained n-channel field-effect transistors (n-FETs) having an embedded Si_1-xGe_x structure that is beneath the Si channel region and which acts as a strain-transfer structure (STS). The Si_1-xGe_x STS has lattice interactions with both the silicon source and drain regions and with the overlying Si channel region. This effectively results in a transfer of lateral tensile strain to the Si channel region for electron mobility enhancement. The mechanism of strain transfer is explained. Significant drive current I_on enhancement of 18% at a fixed off-state leakage I_off of 100 nA/mum is achieved, which is attributed to the strain-induced mobility enhancement. Furthermore, continuous downsizing of transistors leads to higher I_on enhancement in the strained n-FETs, which is consistent with the increasing transconductance G_m improvement when the gate length is reduced.     

Improved low temperature characteristics of P-channel MOSFETs withSi1-xGex raised source and drain

P-channel metal-oxide-semiconductor field-effect transistors with Si_1-xGe_x raised source and drain (RSD) have been fabricated and further studied for low temperature applications. The Si _1-xGe_x RSD layer was selectively grown by ANELVA SRE-612 ultra-high vacuum chemical vapor deposition (UHVCVD) system. Compared to devices with conventional Si RSD, improved transconductance and specific contact resistance were obtained, and these improvements become even more dramatic with reducing channel length. Well-behaved short channel characteristics with reduced drain-induced barrier lowering (DIBL) and off-state leakage current are demonstrated on devices with 100 nm Si_1-xGe_x RSD, due to the resultant shallow junction and less implantation damage. Moreover, temperature measurements reveal that Si_1-xGe_x RSD devices show more dramatic improvement in device performance at low temperature (-50 °C) operation, which can be ascribed to the higher temperature sensitivity of the Si_1-xGe_x sheet resistance     

Si/Si1-xGex heterojunction bipolartransistors produced by limited reaction processing

Si/Si_1-xGe_x heterojunction transistors (HBTs) fabricated by a chemical vapor deposition (CVD) technique are reported. A rapid thermal CVD limited-reaction processing (LRP) technique was used for the in situ growth of all three device layers, including a 20-mm Si_1-xGe_x layer in the base. The highest current gains observed (β=400) were for a Si/Si_1-x Ge_x HBT with a base doping of 7×10¹⁸ cm^-3 near the junction and a shallow arsenic implant to form ohmic contacts and increase current gain. Ideal base currents were observed for over six decades of current and the collector current remained ideal for nearly nine current decades starting at 1 pA. The bandgap difference between a p-type Si layer doped to 5×10¹⁷ cm^-3 and the Si_1-xGe_x(x=0.31) base measured 0.27 eV. This value was deduced from the measurements of the temperature dependence of the base current and is in good agreement with published calculations for strained Si_1-xGe_x layers on Si     

Electron mobility enhancement in strained-Si n-typemetal-oxide-semiconductor field-effect transistors

Enhanced performance is demonstrated in n-type metal-oxide-semiconductor field-effect transistors with channel regions formed by pseudomorphic growth of strained Si on relaxed Si_1-xGe_x. Standard MOS fabrication techniques were utilized, including thermal oxidation of the strained Si. Surface channel devices show low-field mobility enhancements of 80% at room temperature and 12% at 10 K, when compared to control devices fabricated in Czochralski Si. Similar enhancements are observed in the device transconductance. In addition, buried channel devices show peak room temperature mobilities about three times that of control devices     

Si/Si1-x-yGexCy/Si heterojunctionbipolar transistors

We report the first Si/Si_1-x-yGe_xC_y /Si n-p-n heterojunction bipolar transistors and the first electrical bandgap measurements of strained Si_1-x-yGe_x C_y on Si (100) substrates. The carbon compositions were measured by the shift between the Si_1-x-yGe_xC_y and Si_1-xGe_x X-ray diffraction peaks. The temperature dependence of the HBT collector current demonstrates that carbon causes a shift in bandgap of +26 meV/%C for germanium fractions of x=0.2 and x=0.25. These results show that carbon reduces the strain in Si_1-x Ge_x at a faster rate than it increases the bandgap (compared to reducing x in Si_1-xGe_x), so that a Si _1-x-yGe_xC_y film will have less strain than a Si_1-xGe_x film with the same bandgap     

Design, fabrication, and analysis of SiGeC heterojunction PMOSFETs

We present the evaluation of the strain-stabilizing capabilities of C in the Si_1-xGe_x system. To demonstrate these effects, we have designed Si_1-x-yGe_xC_y heterojunction PMOSFET devices over a range of Ge concentrations, with thicknesses that would typically result in related or metastable films under normal processing conditions. The dc characteristics of Si_1-x-yGe_xC_y, SiCe, and Si PMOSFETs (L=10 μm) were evaluated at room temperature and at 77 K. In general, the saturation mobility in Si_1-x-yGe_xC_y devices is higher than that of Si_1-xGe_x and Si devices at low gate bias and room temperature. This enhancement is attributed to the strain stabilization effect of C. With proper optimization of Ge and C concentrations, it is possible to fabricate devices with significant improvements in drive current under normal operating conditions (0-3 V, 300 K). This application of Si_1-x-y Ge_xC_y in PMOSFETs demonstrates the potential benefits of using of C in the Column IV heterostructure system     

The effects of base dopant outdiffusion and undopedSi1-xGex junction spacer layers in Si/Si1-xGex/Si heterojunction bipolar transistors

The effects of base dopant outdiffusion and nominally undoped Si _1-xGe_x spacer layers at the junction interfaces of Si/Si_1-xGe_x/Si n-p-n heterojunction bipolar transistors (HBTs) have been studied. It has been found that small amounts of boron outdiffusion from heavily doped bases of nonabrupt interfaces cause parasitic barriers in the conduction band, which drastically reduce the collector current enhancement in the HBTs. Undoped interface spacers can remove the parasitic barriers, resulting in a strongly improved collector current enhancement     

High performance Si/Si1-xGex resonanttunneling diodes

Resonant tunneling diodes (RTDs) with strained i-Si_0.4Ge_0.6 potential barriers and a strained i-Si quantum well, all on a relaxed Si_0.8Ge_0.2 virtual substrate were successfully grown by ultra high vacuum compatible chemical vapor deposition and fabricated using standard Si processing methods. A large peak to valley current ratio of 2.9 and a peak current density of 4.3 kA/cm² at room temperature were recorded from pulsed and continuous dc current-voltage measurements, the highest reported values to date for Si/Si_1-xGe_x RTDs. These dc figures of merit and material system render such structures suitable and highly compatible with present high speed and low power Si/Si_1-xGe_x heterojunction field effect transistor based integrated circuits     

Silicide/strained Si1-xGex Schottky-barrierinfrared detectors

By employing a thin silicon sacrificial cap layer for silicide formation, the authors successfully demonstrated Pd₂Si/strained Si_1-xGe_x Schottky-barrier infrared detectors with extended cutoff wavelengths. The sacrificial silicon eliminates the segregation effects and Fermi level pinning which occur if the metal reacts directly with Si_1-x Ge_x alloy. The Schottky barrier height of the silicide/strained Si_1-xGe_x detector decreases with increasing Ge fraction, allowing for tuning of the detector's cutoff wavelength. The cutoff wavelength was extended beyond 8 μm in PtSi/Si _0.85Ge_0.15 detectors. It is shown that high quantum efficiency and near-ideal dark current can be obtained from these detectors     

The scaled performance of Si/Si1-xGexresonant tunneling diodes

Small area resonant tunneling diodes (RTDs) with strained Si_0.4Ge_0.6 potential barriers and a strained Si quantum well grown on a relaxed Si_0.8Ge_0.2 virtual substrate were fabricated and characterized. A room temperature peak current density (J_P) of 282 kA/cm² with a peak to valley current ratio (PVCR) of 2.43 were recorded for a 5×5 μm ² sample, the highest values reported to date for Si/Si_1-xGe_x RTDs. Scaling of the device size demonstrated a decrease in J_P proportional to an increase in the lateral area of the tunnel junctions, whereas the PVCR remained approximately constant. This observation suggests that the dc behavior of such Si/Si_1-xGe_x RTD design is presently limited by thermal effects     

Suppression of boron penetration in p-channel MOSFETs usingpolycrystalline Si1-x-yGexCy gatelayers

Boron penetration through thin gate oxides in p-channel MOSFETs with heavily boron-doped gates causes undesirable positive threshold voltage shifts. P-channel MOSFETs with polycrystalline Si_1-x-yGe_xC_y gate layers at the gate-oxide interface show substantially reduced boron penetration and increased threshold voltage stability compared to devices with all poly Si gates or with poly Si_1-xGe gate layers. Boron accumulates in the poly Si_1-x-yGe_xC_y layers in the gate, with less boron entering the gate oxide and substrate. The boron in the poly Si_1-x-yGe_xC_y appears to be electrically active, providing similar device performance compared to the poly Si or poly Si_1-xGe_x gated devices     

A gate-quality dielectric system for SiGe metal-oxide-semiconductordevices

The authors present a high-quality dielectric system for use with Si_1-xGe_x alloys. The system employs plasma-enhanced chemical vapor deposited (PECVD) SiO₂ on a thin (6-8-nm) layer of pure silicon grown epitaxially on the Si_1-x Ge_x layer. The buffer layer and the deposited oxide prevent the accumulation of Ge at the oxide-semiconductor interface and thus keep the interface state density within acceptable limits. The Si cap layer leads to a sequential turn-on of the Si_1-xGe_x channel and the Si cap channel as is clearly observed in the low-temperature C-V curves. The authors show that this dual-channel structure can be designed to suppress the parasitic Si cap channel. The MOS capacitors are also used to extract valence-band offsets     

Gate Influence on the Layout Sensitivity of $ hbox{Si}_{1 - x}hbox{Ge}_{x} hbox{S/D}$ and $hbox{Si}_{1 - y}hbox{C}_{y} hbox{S/D}$ Transistors Including an Analytical Model

We present a simulation study on the effect of the gate module on the channel stress in Si_1-xGe_x and Si_1-yC_y S/D MOS transistors. Stiff gate materials, such as titanium nitride, lead to a decreased channel stress, while a replacement-gate scheme allows the increase of the effectiveness of the Si_1-xGe_x and Si_1-yC_y S/D techniques significantly, independent of the gate material used. The drawback of using a replacement gate is that the channel stress becomes more sensitive to layout variations. In terms of effect on Si_1-xGe_x/Si_1-yC_y S/D stress generation, using a thin metal gate capped by polysilicon is similar to a full metal gate if the thin metal gate thickness exceeds 10 nm. Even metal gates as thin as 1 nm have a clear influence on the stress generation by Si_1-xGe_x/Si_1-yC_y S/D. Removing and redepositing the polysilicon layer while leaving the underlying metal gate unchanged increases the stress, although not to the same extent as for complete gate removal. A simple analytical model that estimates the stress in nested short-channel Si_1-xGe_x and Si_1-yC_y S/D transistors is presented. This model includes the effect of germanium/carbon concentration, active-area length, as well as the effect of gate length and the Young's modulus of the gate. Good qualitative agreement with 2-D finite element modeling is demonstrated.     

Electrical and material quality ofSi1-xGex/Si p-N heterojunctions produced bylimited reaction processing

Si_1-xGe_x/Si p-N heterojunctions prepared by a chemical vapor deposition technique, limited reaction processing (LRP) were characterized using DC electrical measurements, transmission electron microscopy (TEM), and X-ray topography. Heterojunctions with Si _1-xGe_x layer thickness ranging from 52 to 295 nm and a constant Ge fraction of 23% were fabricated to study the effect of increasing the number of misfit dislocations on the device characteristics. Devices with the thinnest layers (⩽120 nm) display forward characteristics with ideality factors of 1.01 and reverse leakage current densities of less than 4 nA/cm for a 5-V reverse bias. These thin-layer devices have dislocation spacings greater than 10 μm. Devices utilizing Si_1-xGe_x layers thicker than 200 nm have forward characteristics which clearly display the presence of recombination currents, and reverse leakage current densities greater than 290 nA/cm² at -5 V. The dislocation spacing in these devices is less than 1 μm. Ideal characteristics were found at room temperature in devices known to contain dislocations     

Characteristics of p- and n-channelpoly-Si/Si1-xGex/Si sandwiched conductivitymodulated thin-film transistors

Both p- and n-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistors (CMTFTs) are demonstrated and experimentally characterized. The transistors use a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide a high on-state current. Results show that the transistors provide a high on-state current as well as a low leakage current compared to those of conventional offset drain TFTs. The p- and n-channel CMTFTs can be combined to form CMOS drivers, which are very suitable for use in low temperature large area electronic systems on glass applications     

Electron mobility enhancement in strained-Si n-MOSFETs fabricatedon SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si_1-xGe_x-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si_0.75Ge_0.26 and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si_1-xGe_x layer     

Evaluation of the valence band discontinuity ofSi/Si1-xGex/Si heterostructures by application ofadmittance spectroscopy to MOS capacitors

In this study, admittance spectroscopy is applied for the first time to MOS capacitors fabricated on Si/Si_1-xGe_x/Si double-heterostructures, in order to evaluate the valence band discontinuity ΔE_v at the Si/Si_1-xGe_x interface. The principle of the measurement is presented and verified by the experimental results. A new feature of admittance spectroscopy applied to MOS capacitors is the ability to select the interface whose barrier is measured, by controlling the gate voltage. This fact is confirmed by the measurement of MOS capacitors, which include a SiGe well with different Ge contents at the front and the back interfaces. It is found from this measurement that, while ΔE_v at the back interface of the double-heterostructure is measured under slight depletion conditions for MOS capacitors, ΔE_v averaged between the front and the back interfaces is measured under accumulation conditions. The Ge_x content dependence of the measured ΔE_v is found to be in fairly good agreement with the theoretical values     

Numerical simulation and comparison of Si BJTs andSi1-xGex HBTs

Using the Monte Carlo method for the solution of the Boltzmann transport equation, the authors analyze the low-field carrier mobilities of strained layer and bulk Si and Si_1-xGe_x alloys. Strained alloy layers exhibit higher low-field mobility compared with bulk Si at doping levels >10¹⁸ cm^-3 and for a Ge mole fraction x⩽0.2, while the unstrained alloy bulk low-field mobility is always lower than that of Si for any doping level or mole fraction. These mobilities are then used in a two-dimensional drift-diffusion equation solver to simulate the performance of Si BJTs (bipolar junction transistors) and Si_1-xGe_x HBTs (heterojunction bipolar transistors). The substitution of a Si_0.8 Ge_0.2 layer for the base region leads to a significant improvement in current gain, turn-on voltage, and high-frequency performance. Maximum unity current gain frequency f_T increases two times over that of an Si BJT if the bulk alloy mobility is used for the alloy base layer; it increases three times if strained-layer mobility is used. Maximum frequency of oscillation also improves, but not as dramatically as f_T     

A p-channel poly-Si/Si1-xGex/Si sandwichedconductivity modulated thin-film transistor

A p-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistor (CMTFT) is proposed and demonstrated in this paper for the first time. This structure uses a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide high on-state current. Results show that this structure provides high on-state current as well as low leakage current as compared to that of conventional offset drain TFTs. The on-state current of the structure is 1.3-3 orders of magnitude higher than that of a conventional offset drain TFT at a gate voltage of -24 V and drain voltage ranging from -15 to -5 V while maintaining comparable leakage current