低阈值电压控制技术

本文论述了在标准1．0微米CMOS工艺线基础上开发的1～1．2微米工艺的阈值电压影响因素，对阈值电压的几种控制方法进行了分析比较，探讨了低阈值电压（0．5V左右）的控制，并介绍了如何根据电路的需要来选取阈值电压的控制方法。     

1.25Gbps串并并串转换接收器的低抖动设计

对1.25Gbps应用于千兆以太网的低抖动串并并串转换接收器进行了设计,应用了带有频率辅助的双环时钟数据恢复电路,FLL扩大了时钟数据恢复电路的捕捉范围。基于三态结构的鉴频鉴相从1.25Gbps非归零数据流中提取时钟信息,驱动一个三级的电流注入环形振荡器产生1.25GHz的低抖动时钟。从低抖动考虑引入了均衡器。该串并并串转换接收器采用TSMC0.35μm2P3M3.3V/5V混合信号CMOS技术工艺。测试结果表明了输出并行数据有较好的低抖动性能:1σ随机抖动(RJ)为7.3ps,全部抖动(TJ)为58mUI。     

面向低强度无线网络信号接收器的设计与实现

以往设计的低强度无线网络信号接收器,均无法有效对环境干扰与低强度无线网络的传输性质进行协调,导致接收信号不完整、且接收距离较近,故设计高性能的面向低强度无线网络信号接收器,其由基准源电路、动态增益放大器和信号检测电路组成。基准源电路自动校准动态增益放大器和信号检测电路产生的电路参数,维持接收器的正常工作。动态增益放大器对低强度无线网络信号进行自动增益调节,经其增益调节后的低强度无线网络信号将传输给信号检测电路进行唤醒。唤醒成功后,信号检测电路将电路中的所有信号和电路参数传输给基准源电路进行处理,基准源电路的输出信号即为用户接收到的最终信号。信号接收器的实现部分给出了接收器的接收谱估计函数、低强度无线网络信号接收流程图。经实验验证可知,所设计的接收器接收完整性较强,并拥有较远的接收距离。     

一种应用于高速数据通信的LVDS接收器设计

提出了一种应用于高速数据通讯的低电压差分信号(LVDS)接收器电路设计,符合IEEEStd.1596.3-1996(LVDS)标准,有效地解决了传统电路在低电源电压下不能满足标准对宽共模范围的要求以及系统的高速低功耗要求。电路采用65nm 1P9M CMOS Logic工艺设计实现,仿真结果表明该接收器电路能在符合标准的0V-2.4V的宽输入共模电平下稳定工作,在电源电压为2.5V的工作条件下,数据传输速率可以达到2Gbps,平均功耗仅为3mW。     

串行低压差分信号接收器设计

设计了一种内置差分信号有效性检测电路的串行低压差分信号接收器,通过对信号的差分摆幅进行比较,能够正确检测差分信号是否处于标准范围之内.采用片内阻抗匹配网络和镜像补偿型差分电路结构实现了高速串行差分信号到CMOS电平信号的转换,也克服了高速信号传输过程中的信号完整性问题.基于0.13μm CMOS混合信号工艺设计,仿真结果表明,所设计的电路能够正确检测和接收数据率高达2.5 Gb/s,差分摆幅超过200 mV的串行差分信号.     

一种低延时、低功耗电压比较器

设计了一种用于大动态范围CMOS图像传感器的OTA(运算跨导放大器)低功耗、低延时电压比较器.该电压比较器以标准OTA电路为基础,使用了非对称的拓扑结构.用0.6 μm DPDM标准数字CMOS工艺参数仿真,在3.3 V供电电源下,功耗2.0 μw,电路最小延时9 ns.将该电压比较器应用到大动态范围图像传感器读出电路中,实现了预期目标.     

低频段自适应梳状滤波器的研制

滤波器电路是信号处理系统中的重要器件，自适应梳状滤波器是滤波器本身根据输入信号选择滤波器通路的一种电路，它大大减小了滤波器的带通宽度，降低了器件噪声，提高了信号接收器的精度。该文中设计的自适应梳状滤波器是由六波段滤波器组成，接收信号的频率为3kHz～120kHz，降噪范围是单一滤波器的1／6～1／5。     

一种相位准确度高幅值失配度低的正交LO驱动电路

提出了一种工作在1.1～1.2GHz的相位准确度高、幅值失配度低的正交LO驱动电路．它主要由高频放大器、二阶的无源多项滤波器、相位和幅度校准电路（PMCC）组成．PMCC是一种利用前馈技术实现的低功耗电路，大大提高了正交信号的正交性，降低了相邻支路信号的幅值误差．仿真结果表明，经过PMCC校准后，输出正交信号的相位误差可以降低大约一半，而幅度误差可以降低到原来的十分之一．PMCC可直接驱动混频器，无需额外的驱动电路．本设计已经用TSMC 0.25μm CMOS工艺实现并进行了验证．测试结果表明本文提出的校准电路能够获得高正交性（＜２°＝和低幅值误差（＜０.１％＝的正交信号，测试的最大功率增益为5.25dB，在2.5V的电源电压下，消耗的电流约为6mA，芯片面积为1.0mm×1.0mm．     

微波低噪放大器的原理与维护

微波低噪放大器作为微波接收系统的前端放大器,要求它具有尽可能低的噪声系数,以提高接收门限,同时要求它具有一定大的功率增益以便降低噪声性能。为此常常采用多级放大器组联。其组成方框图：1低噪放大器的原理（1）输入端接最小噪声系数设计,提供一个匹配网络变换成已知的最佳源反射系数。（2）输出端按最大增益设计,以便有最大的增益。（3）偏置电路低噪声放大器要求在相当低的漏极电流下工作而漏极电压时噪声影响不灵敏,考虑功耗漏电压不宜过高,一般工作点为V。－2～3V,IDS／IDSS＝0．15,IDS一般10mA同时,由于栅极电压…     

低照度CMOS图像传感器设计与实现

设计了一种基于电容反馈跨阻放大器型（Capacitive Trans-impedance Amplifier,CTIA）像元电路与双采样（Delta Double Sampling,DDS）的低照度CMOS图像传感器系统。采用CTIA像元电路提供稳定的光电二极管偏置电压以及高注入效率,完成在低照度情况下对微弱信号的读取;同时采用数字DDS结构,通过在片外实现像元积分信号与复位信号的量化结果在数字域的减法,达到抑制CMOS图像传感器中固定图案噪声的目的,进一步提高低照度CIS的成像质量。基于0.35 m标准CMOS工艺对此基于CTIA像元电路的CMOS图像传感器芯片进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明该低照度CMOS图像传感器系统可探测到0.05 lx光照条件下的信号。     

一个0.18μm高速低功耗的发送和接收电路

提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它町以工作到1.6Gb/s.芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s,同时发送和接收端的功耗分别是35和6mW.     

一个0.18μm高速低功耗的发送和接收电路

提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它町以工作到1.6Gb/s.芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s,同时发送和接收端的功耗分别是35和6mW.     

LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively     

Design of high speed LVDS transceiver ICs

The design of low-power LVDS(low voltage differential signaling) transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/s.For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers.In addition,the LVDS receiver also supports ...     

一种CMOS图像传感器片上LVDS驱动电路设计

为满足CMOS图像传感器(CIS)图像数据高速输出的需求,提出一种适用于CIS的片上高速低电压差分信号(LVDS)驱动电路结构。首先介绍了CIS高速数据传输接口的常见类型、LVDS接口技术的起源和特点;接着根据CIS的需求特点确定了LVDS驱动电路的设计思路和结构;最后给出了驱动电路设计原理图和仿真结果,以及接收端眼图仿真结果。仿真结果表明,该LVDS驱动电路,数据传输速率可以达到500Mb/s,所有参数均满足TIA/EIA-644A接口标准的需求,接收端眼高为310mV,眼宽为0.9UI。     

Performance analysis on DPSK modulation using symbol repetition and interleaving

It is well known that the differential phase shift keying (DPSK) transmission does not require a reference phase and reduces the computational complexity and power consumption of the receiver at the cost of the transmission reliability. To improve the reliability of transmission under such scenario, we use a symbol repetition scheme to the DPSK modulation, such as the IEEE 802.15.6 wireless body area network and the ITU‐T G.9903. However, the message symbol repetition with interleaving in conventional manner as in coherent modulation schemes may degrade the receiver performance because of the noise characteristic of the differential demodulation structure. In this work, we analyze the performance of repeated DPSK system with and without the interleaver and demonstrate which scenario is suitable for each modulation order. We propose a proper transmission setting, which achieves noticeable performance improvement at the receiver as well as enhances the energy efficiency of the communication system. Since it can be implemented with very small modification to existing systems, our results are highly applicable with negligible modification of the hardware structure and thus enable substantially low‐cost implementation in future communication systems including wireless body area network internet of things applications.     

Performance evaluation of optical OFDM in direct detected systems based on MZM bias and drive voltages

The impact of DC bias and the RF drive voltage of the dual electrode Mach Zehnder Modulator (DE-MZM) on the transmission performance of optical orthogonal frequency division multiplexing (O-OFDM) direct detected systems is analyzed theoretically and verified by simulation. Selection of optimum bias and drive voltage is necessary to minimize the optical signal to noise ratio (OSNR) requirements and the non-linear distortions in the fiber transmission. In this paper, we compare MZM modulation techniques such as double sideband full carrier and single sideband (SSB) [biased at quadrature and minimum power transmission (MPT) point] with a novel modified SSB OFDM technique. To the best of our knowledge for the first time, a mathematical model for above modified SSB technique is developed to evaluate the OSNR requirement, chromatic dispersion of the fiber, spectral efficiency and the receiver sensitivity against other modulation techniques. Our results show that the modified SSB technique provides high spectral efficiency, receiver sensitivity and low chromatic dispersion against other the modulation techniques, while the one biased at MPT minimizes the OSNR requirements.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende...     

增益可控CMOS低噪声放大器

设计了采用SMIC0.18μm RF CMOS工艺的共源共栅NMOS结构的增益可变的差动式低噪声放大器。在考虑了ESD保护pad和封装寄生效应后,着重对低噪声放大器的输入阻抗匹配、增益以及共源共栅级联结构下的噪声系数、线性度等进行了一系列分析,并提出了优化措施。芯片测试结果表明:在1.56GHz中心频率下,-3dB带宽约为150MHz,输出最大电压增益为27dB,此时噪声系数NF约为2.33dB,IIP3约为4.0dBm,可变增益范围为7dB。在3.3V电源电压下消耗电流8.2mA。此设计方法可以应用到诸如GSM、GPS等无线接收机系统中。