ORC的代码生成的关键技术

处理机的指令级并行能力只有通过编译器才得以发挥。代码生成是编译器后端中直接针对目标处理机的优化阶段的集合，因而它是提高目标处理机指令级并行的重要组成部分。ORC(Open Research CompiLer)是一款针对IA-64体系结构的开放源码编译器，它具有丰富的优化阶段和良好的性能。本文介绍了ORC的代码生成的关键技术，这些技术包括区域构造、谓词相关优化、全局指今调度、参数化的机器描述以及微调度。实测结果表明，这些技术取得了显著的优化结果，ORC相对于Pro64能取得平均23％的加速比。     

基于插桩技术的并行程序性能分析方法设计和实现*

介绍了一种异构环境下的并行调试及性能分析工具ParaVT的设计方法和实现.通过对并行程序源代码的分析处理,利用自动插桩模板插入用于调试和性能分析的用户代码,从而对并行程序进行断点调试和性能参数收集,达到进一步优化程序设计的目的.     

嵌入式系统调试方法的分析与比较

调试是嵌入式系统开发过程中必不可少的重要环节,它占整个开发时间的20%～50%.本文对常用的调试方法进行了介绍,分析与比较了调试方法及其调试工具的特点,为在不同条件下选择合适的调试工具提供了参考,有助于嵌入式系统调试性能的提高.     

多计算机的自动插桩与监测系统

在设计大规模的并行应用程序时,如何使多处理器的利用率达到最优,这对程序设计人员来讲是一个很大的挑战。一般说来,由于应用程序在运行时性能上的缺陷,计算资源得不到充分利用。因此,迫切需要对应用程序进行“性能调试”,即在正确性的基础上,通过揭示这些缺陷,对程序进行细调而提高程序性能。在这篇文章里,介绍了一个软件工具包—自动插桩和监测系统(theAutomatedInstrumentationandMonitoringSystem),它集程序插桩、运行监测和性能分析为一体,支持在多处理器上对并行应用程序进行性能评估。文章首先论述了一些建立性能调试工具的基本问题;然后,详细描述AIMS系统的体系结构以及在利用AIMS工具包进行性能调试工具的开发中的经验;最后,使用两个例子详细地描述使用AIMS系统进行性能调试的过程。     

通用多核并行调试方法研究

多核体系结构加深了并行编程的难度。为开发高效的多核并行调试工具,本文分析了传统并行调试技术面临的问题,提出按并行粒度分级的调试方法,该方法可充分利用并行编程的经验,不断优化调试技术。     

龙芯/ORC编译器中的Edge Profiling技术

在程序实际执行中，Profiling技术能为编译器提供准确的轮廓信息。编译优化借助这种轮廓信息，可在优化时进行取舍，提高生成代码性能。该文介绍了在龙芯/ORC编译器中edge profiling的技术，给出了在edge profiling辅助下CPU2000性能测试结果。     

一种实用的并行程序可视化性能分析方法

并行程序由于自身的复杂性使得并行程序的调试相比串行程序要困难的多，因此用可视化的性能分析工具来辅助并行程序的调试显得非常重要，以此来帮助程序员找到程序的性能瓶颈，为并行程序的优化提供指导和建议。本文在研究MPE性能分析机理的基础上，介绍了一种实用的MPI并行程序可视化性能分析方法，并用实例详细说明了并行程序实时可视化性能分析和事后可视化性能分析过程。     

程序调试、监测与性能分析的一体化工具*

随着高性能芯片及高性能计算的应用,人们对调试器的要求不再仅局限于“正确性调试”,而是更进一步要求进行“性能调试”,即在正确性的基础上,通过对程序的细调而获得最佳性能.正确性调试和性能调试通常由独立的工具支持,这种模式已不能很好地支持高性能计算.介绍了一个为高性能SIMD芯片设计的同时具有正确性调试和性能调试功能的可视化工具.它集程序调试、行为监测和性能分析为一体,改善了高性能程序的开发周期,为高性能计算提供了强有力的支持.     

支持有向有环图的微调度方法

指令调度是编译器中的重要优化阶段．如何充分利用处理器结构相关的资源,发掘程序并行性,以提高编译优化性能和增强代码可适应性,一直是指令调度的研究难点之一．目前微调度已经取得了一定的效果,但对软件流水产生的有向有环图则未能提供支持．在ORC中提出并实现了一种基于IA-64体系结构的支持有向有环图的微调度方法,有效地减少了程序执行周期和流水线停顿,取得了较为满意的编译优化性能．     

CZXT-013操作系统的调试

本文首先讨论了操作系统的可靠性与调试的关系,然后着重介绍了013机操作系统的调试方案,以及在分调阶段和联调阶段使用的两个调试工具——进程测试器和系统监示器。进程测试器是一个供调试进程模块使用的公用调试程序。系统监示器是附加在系统控制中枢的一组信息收集输出程序。     

基于GCC的VLIW编译系统研究

VLIW机器在单个机器周期中同时发射并执行多个的并行操作,从而获得较高的指令级并行度,这些操作之间的依赖分析和调度工作则被完全交给相应的编译器执行,因此VLIW的并行性能能否充分发挥取决于VLIW体系结构相关编译器的质量。GNU开发的GCC是被最广泛使用的编译系统之一,它具有多语言、多平台支持的能力和开放的结构,能够运用各种成熟的常规编译优化技术生成高效的代码。文章分析了VLIW及GCC的结构特点,提出了一种基于GCC的VLIW编译系统设计方案,利用GCC进行RTL中间代码一级的体系结构无关优化和少量体系结构相关优化,在汇编代码一级针对VLIW结构进行体系结构相关的优化,从而充分利用GCC的成熟编译技术快速开发高效的VLIW多语言编译系统。     

Compiling Fortran 90D/HPF for Distributed Memory MIMD Computers

This paper describes the design of the Fortran90D/HPF compiler, a source-to-source parallel compiler for distributed memory systems being developed at Syracuse University. Fortran 90D/HPF is a data parallel language with special directives to specify data alignment and distributions. A systematic methodology to process distribution directives of Fortran 90D/HPF is presented. Furthermore, techniques for data and computation partitioning, communication detection and generation, and the run-time support for the compiler are discussed. Finally, initial performance results for the compiler are presented. We believe that the methodology to process data distribution, computation partitioning, communication system design, and the overall compiler design can be used by the implementors of compilers for HPF.     

A methodology and notation for compiler front end design

A methodology and associated notation for designing compiler front ends, and in particular the interface between the parser and the semantic routines, is described. The methodology leads to a clean, easy to understand, documentable design. The notation is similar to an attribute grammar, but its purpose is to document the first pass of a specific compiler, rather than to describe the semantics of a language. It is designed to be accessible to non-specialists, easy to learn, and natural. It can be used with or without software support. The notation was used during the development of a large compiler, and to assist in the transfer of the compiler to the group that will maintain it. Experience with the notation indicates that it meets its goals.     

Characterizing distributed shared memory performance: a case studyof the Convex SPP1000

In a distributed shared memory (DSM) multiprocessor, the processors cooperate in solving a parallel application by accessing the shared memory. The latency of a memory access depends on several factors, including the distance to the nearest valid data copy, data sharing conditions, and traffic of other processors. To provide a better understanding of DSM performance and to support application tuning and compiler development for DSM systems, this paper extends microbenchmarking techniques to characterize the important aspects of a DSM system. We present an experiment-based methodology for characterizing the memory, communication, scheduling, and synchronization performance, and apply it to the Convex SPP1000. We present carefully designed microbenchmarks to characterize the performance of the local and remote memory, producer-consumer communication involving two or more processors, and the effects on performance when multiple processors contend for utilization of the distributed memory and the interconnection network     

Design and implementation of Java just-in-time compiler

Early Java implementations relied on interpretation,leading to poor performance compared to compiled programs,Java just-in-time(JIT) compiler can compile Java programs at runtime,so it not only improves Java‘s performance prominently,but also preserves Java‘s portability.In this paper the design and implementing techniques of Java JIT complier based on Chinese open system are discussed in detail.To enhance the portability,a translating method which combines the static simulating method and macro expansion method is adopted.The optimization technique for JIT compiler is also discussed and a way to evaluate the hotspots in Java programs is presented.Experiments have been conducted to verify JIT compilation technique as an efficient way to accelerate Java.     

Evaluating the impact of the simulation environment on experimentation results

Simulation has become the tool of choice for advanced computer architecture research. Simulation model abstraction as well as compiler specifics can have significant impact on the observed performance trends and may lead to incorrect conclusions. This study presents a methodology that compares the predicted performance impact of several architectural techniques measured on a variety of simulator and compiler configurations. A significant difference in speedup between experiments indicates that a technique is sensitive to this particular variation. The results demonstrate a strong but non-uniform relationship between modeling abstraction and measurement error, as well as a significant sensitivity to the compiler.     

The compiler as a validation and evaluation tool

Like a processor executes flawlessly at different frequencies, a compiler should produce correct results at any optimization level. The Intel^® Itanium^® processor family with its new features, like the register stack engine and control- and data speculation, provides new and unique challenges for ported software and compiler technology. This paper describes validation and evaluation techniques that can be employed in compilation tools and can help to get a cleaner port of an application, a more robust compilation system and even insights into performance tuning opportunities. Using Itanium as a specific example, the paper explains why the register stack engine (RSE), the large register file, or control- and data speculation can potentially expose bugs in poorly written or compiled software. It then demonstrates validation and evaluation techniques to find or expose these bugs. An evaluation team can employ them to find, eliminate and evaluate software bugs. A compiler team can use them to make the compiler more stable and robust. A performance analysis team can use them to uncover performance opportunities in an application. We demonstrate our validation and evaluation techniques on code examples and provide run-time data to indicate the cost of some of our methods.     

AutoConfig: 面向深度学习编译优化的自动配置机制

随着深度学习模型和硬件架构的快速发展,深度学习编译器已经被广泛应用.目前,深度学习模型的编译优化和调优的方法主要依赖基于高性能算子库的手动调优和基于搜索的自动调优策略.然而,面对多变的目标算子和多种硬件平台的适配需求,高性能算子库往往需要为各种架构进行多次重复实现.此外,现有的自动调优方案也面临着搜索开销大和缺乏可解释性的挑战.为了解决上述问题,本文提出了AutoConfig,一种面向深度学习编译优化的自动配置机制.针对不同的深度学习计算负载和特定的硬件平台,AutoConfig可以构建具备可解释性的优化算法分析模型,采用静态信息提取和动态开销测量的方法进行综合分析,并基于分析结果利用可配置的代码生成技术自动完成算法选择和调优.本文创新性地将优化分析模型与可配置的代码生成策略相结合,不仅保证了性能加速效果,还减少了重复开发的开销,同时简化了调优过程.在此基础上,本文进一步将AutoConfig集成到深度学习编译器Buddy Compiler中,对矩阵乘法和卷积的多种优化算法建立分析模型,并将自动配置的代码生成策略应用在多种SIMD硬件平台上进行评估.实验结果验证了AutoConfig在代码生成策略中有效地完成了参数配置和算法选择.与经过手动或自动优化的代码相比,由AutoConfig生成的代码可达到相似的执行性能,并且无需承担手动调优的重复实现开销和自动调优的搜索开销.     

基于编译指示的向量化方法

编译器由于程序分析能力不足,无法自动实现循环向量化或者会造成盲目自动向量化。为此,提出一种基于编译指示的向量化方法。通过在代码中插入向量化编译指示语句,指导自动向量化编译工具的处理过程,自动生成高效的向量化代码。测试结果表明,该方法能够有效提高目标代码的运行性能。     

一种基于统计分析的存储系统性能调优方法

计算机系统参数的合理配置能有效提升应用程序的性能。以NFS网络存储系统为例,提出了一种基于统计分析的存储系统性能调优方法,该方法分为关键系统参数识别和关键参数性能优化两个子阶段。阶段一采用方差分析(ANOVA)来建模系统参数的性能灵敏度,识别出对应用性能有显著影响的关键系统参数;然后在此基础上,阶段二采用响应面分析(RSM)来考察各关键参数对性能响应的影响,并综合前两个子阶段给出了性能调优算法,通过该算法找出系统的最优配置,从而最终达到性能调优的目的。最后,用实验评价了文中方法在Web, E-mail, Fileserver,Linux实用程序以及微基准测试等多种重要应用场景下的性能调优结果,实验结果证实了该调优方法的有效性和实用性。