编码理论、信道理论与技术、编译码器、声码器、密码学、密码术

0623216高速Viterbi译码器的FPGA实现[刊,中]/张健//电讯技术．—2006,46(3)．—37-41(G)提出了一种高速Viterbi译码器的FPGA实现方案。该译码采用全并行结构的加比选模块和寄存器交换法以提高速度,并且利用大数判决准则和对译码器各个部分的优化设计,减少了硬件消耗。译码器的最高输出数据速率可以达到90Mbps。译码器的性能仿真和FPGA实现验证了该方案的可行性。参3 0623217特征3时椭圆曲线与函数域的DLP等价[刊,中]/王佳昱//信息安全与通信保密．—2006,(6)．—84-86(L)论文给出了特征等于3的有限域上,椭圆曲线的有理点群(除去这个点本身)与实二次函数域上的既约主理想之间的一一对应,从而使二者的离散对数问题(DLP)等价。参7     

DTMB中LDPC码编译码器的FPGA实现

针对数字地面多媒体广播标准中的低密度奇偶校验(LDPC)码,设计实现了基于现场可编程逻辑门阵列(FPGA)的LDPC码编译码器。设计所采用的编译码器方案均采用部分并行结构,在吞吐量与硬件复杂度之间达到了较好的折中。进一步,实现了用于LDPC码性能测试的误码测试硬件系统。基于FPGA的硬件实现结果表明,针对码率为0.4的LDPC码,设计的编译码器可工作在160MHz的时钟频率下,以译码前的数据量计算,吞吐量达到214Mbps。当误比特率为10-6时,实现的6比特量化译码器与浮点译码器的性能差距仅为0.05d B。     

信息理论与电子设备

1210 信息理论与技术0524991大约束度 Viterbi 译码器在 FPGA 中的实现[刊,中]/李鹏辉//中国集成电路.—2005,(7).—43-46(C2)本文介绍了针对约束长度为9,码率为1/2卷积码的 Viterbi 译码器在 FPGA 中的一种实现方案。其中采用了串并结合的方法兼顾面积和速度,并用流水线来提高译码速度。测试结果表明,本设计消耗硬件资     

面积优化的RS(255,239)高速译码器的设计与实现

针对基于改进型欧几里德(Modified Euclidean,ME)算法的RS码译码器所存在的不足,提出一种面积优化的欧几里德算法的FPGA实现方案.该方案充分利用改进型欧几里德模块的空闲资源,采用复用的方法将原先的2t个PE模块减少为t个.文章将该面积优化的欧几里德模块应用到RS(255,239)译码器的设计和实现中,以达到减少芯片面积,降低成本的目的.经过仿真和测试,基于此设计的高速并行RS译码器在正确实现译码功能的同时,可以大幅减少硬件资源的占用率,且其吞吐量达到6.4Gbps.     

基于级联码的信道编译码设计与FPGA实现

介绍了RS(255,223)码级联卷积(4,3,3)码编译码器的实现,对于编码和译码端不同的结构特点.分别采用并行和串行结构实现.其中RS译码采用欧几里德算法,卷积译码采用维特比算法.同时给出了该编译码器的FPGA实现,按照自上而下的设计流程,在保证速度的同时最大限度地减少了资源占用.     

RS(255,223)编译码器的设计与FPGA实现

介绍了RS(255,223)编译码器的设计,并根据编译码器的不同特点,采用不同结构的GF(28)乘法器.编码器利用多项式除法,采用并行结构;译码器采用Euclid算法,关键模块采用了串并结合的结构.同时给出了算法的FPGA实现,按照自上而下的设计流程,在保证速度的同时最大限度地减少了资源占用.     

高速Viterbi译码器的FPGA实现

提出了一种高速Viterbi译码器的FPGA实现方案。该译码器采用全并行结构的加比选模块和寄存器交换法以提高速度，并且利用大数判决准则和对译码器各个部分的优化设计，减少了硬件消耗。译码器的最高输出数据速率可以达到90Mbps。译码器的性能仿真和FDGA实现验证了该方案的可行性。     

LDPC译码器的Impulse C编程设计

提出了一种对LDPC码(低密度奇偶校验码)译码器进行FPGA(现场可编程门阵列)设计的新方案.不同于采用传统硬件描述语言方法,该方案基于最新一代从Impulse C编程到硬件编译的便捷技术,在Xilinx Virtex2芯片XC2V2000上实现了1/2码率、码长2500的(3,6)LDPC码译码器.最大迭代次数为10次,主频50 MHz时,数据吞吐量可达10Mbit/s,能够满足第三代移动通信系统对译码速率的要求.     

卷积码Viterbi译码器的FPGA设计与实现

主要介绍了卷积码中Viterbi译码器的FPGA实现方案。方案中设计了幸存路径交换寄存器模块，充分利用FPGA中丰富的触发器资源，减小了译码器状态控制的复杂度，提高了VB译码器的运行速度。     

一种低开销双二元turbo译码器设计

设计一种低开销双二元turbo译码器,提出了一种能够适应滑动窗算法的交织器结构,通过与传统方案中的交织器联合使用,大大降低了交织与解交织过程所需要的存储单元.同时将取模归一化(modulo normalization)技术运用到双二元turbo译码器加比选(ACS)模块的设计上,缩短了关键路径的延时,提高了时钟频率和吞吐量.采用FPGA对译码器进行了验证,提出的译码器和传统的译码器相比,存储资源节省12%,和使用存储器存储交织/解交织地址的译码器相比,存储资源节省97%.     

基于DVD应用的流水线RS-PC解码的VLSI设计

基于DVD数据纠错的应用，设计实现了全程流水线处理的RS-PC解码，采用分解的无逆BM(Berlekamp—Massey)算法和脉动时序控制实现RS解码器的三级流水线处理，采用行列独立的缓冲器和纠错解码器实现行列纠错的两级流水线处理。该RS-PC解码能达到非常快的处理速度，在行列纠错处理无迭代的情况下，数据率可达到每时钟一个字节。     

一种高速自适应Reed-Solomon译码结构及其VLSI优化实现

该文给出了一种自适应Reed-Solomon(RS) 译码器结构。该结构可以自适应地处理长度变化的截短码编码数据块,适合于高速译码处理。该结构使译码处理不受数据块间隙长短的约束,既可以处理独立的编码数据块也可以处理连续发送的编码数据块。另外本译码器结构可以保证输出数据块间隔信息的完整性,满足无线通信和以太网中特殊业务的要求。本文还基于该结构对RS(255,239)译码器予以实现,该译码器经过Synopsys综合工具综合并用TSMC 0.18 CMOS工艺实现,测试结果验证了该译码器的自适应功能和译码正确性,其端口处理速率可达1.6Gb/s。     

A generalized linear quasi-ML decoder of OSTBCs for wireless communications over time-selective fading channels

We propose a novel generalized linear quasi-maximum-likelihood (quasi-ML) decoder for orthogonal space-time block codes (OSTBCs) for wireless communications over time-selective fading channels. The proposed decoder computes the decision statistics based on the channel-state information and completely removes the intertransmit-antenna interference to provide excellent diversity advantage when the channel varies from symbol to symbol. It is shown that when the channel is quasi-static, the proposed decoder is the optimum ML decoder for OSTBCs. The theoretical bit-error probabilities of the proposed decoder are given and it is shown that the proposed decoder does not exhibit error floors at high signal-to-noise ratios like the decoder proposed in and . Simulation results for various channel-fading rates are presented to verify the theoretical analysis.     

Improved decoding of LDPC coded modulations

A coded modulation belief propagation (CMBP) decoder is proposed for decoding LDPC codes with multilevel modulations. The decoder takes into account statistical dependencies among bits originating in the same symbol, providing better performance than the marginal BP (MBP) decoder. Asymptotically it converges to MAP decoding. The CMBP decoder is based on a single-level coding (SLC) scheme and does not suffer from practical disadvantages of multi-level coding (MLC) schemes. Furthermore, the CMBP decoder can close the capacity gap of the bit interleaved coded modulation (BICM) SLC scheme. The BICM capacity gap increases when the modulation size increases and in scenarios where gray mapping is not possible.     

Universal decoding for frequency-selective fading channels

We address the problem of universal decoding in unknown frequency-selective fading channels, using an orthogonal frequency-division multiplexing (OFDM) signaling scheme. A block-fading model is adopted, where the bands' fading coefficients are unknown yet assumed constant throughout the block. Given a codebook, we seek a decoder independent of the channel parameters whose worst case performance relative to a maximum-likelihood (ML) decoder that knows the channel is optimal. Specifically, the decoder is selected from a family of quadratic decoders, and the optimal decoder is referred to as a quadratic minimax (QMM) decoder for that family. As the QMM decoder is generally difficult to find, a suboptimal QMM decoder is derived instead. Despite its suboptimality, the proposed decoder is shown to outperform the generalized likelihood ratio test (GLRT), which is commonly used when the channel is unknown, while maintaining a comparable complexity. The QMM decoder is also derived for the practical case where the fading coefficients are not entirely independent but rather satisfy some general constraints. Simulations verify the superiority of the proposed QMM decoder over the GLRT and over the practically used training sequence approach.     

The TAR decoder-a bandpass Viterbi/FFT decoder for convolutionalencoded spread-spectrum signals

A new form of bandpass convolutional decoder termed the TAR decoder is presented. The decoder has as its basis the classic Viterbi algorithm, but uses a fast Fourier transform (FFT) in order to cope with a frequency offset, phase rotating, received signal. The TAR decoder also uses a two-dimensional (2-D) despread signal history array in addition to the usual path history registers. The advantage of the TAR decoder is that the decoder does not need to be preceded by a modem and is not subject to the problems of cycle slips. It can operate at negative input signal-to-noise ratio (SNR) values and is well suited to the decoding of low rate convolutional codes as may be used in code-division multiple-access (CDMA) systems. Symbol timing recovery is still required but this is straightforward in practical cases down to ≃-15 dB SNR     

5G LDPC码译码器实现

该文介绍了5G标准中LDPC码的特点,比较分析了各种译码算法的性能,提出了译码器实现的总体架构：将译码器分为高速译码器和低信噪比译码器。高速译码器适用于码率高、吞吐率要求高的情形,为译码器的主体;低信噪比译码器主要针对低码率、低信噪比下的高性能译码,处理一些极限情形下的通信,对吞吐率要求不高。分别对高速译码器和低信噪比译码器进行了设计实践,给出了FPGA综合结果和吞吐率分析结果。     

Twin-stack decoding of recursive systematic convolutional codes

We present a method for soft-in/soft-out sequential decoding of recursive systematic convolutional codes. The proposed decoder, the twin-stack decoder, is an extension of the well-known ZJ stack decoder, and it uses two stacks. The use of the two stacks lends itself to the generation of soft outputs, and the decoder is easily incorporated into the iterative “turbo” configuration. Under thresholded decoding, it is observed that the decoder is capable of achieving near-maximum a posteriori bit-error rate performance at moderate to high signal-to-noise ratios (SNRs). Also, in the iterative (turbo) configuration, at moderate SNRs (above 2.0 dB), the performance of the proposed decoder is within 1.5 dB of the BCJR algorithm for a 16-state, R=1/3, recursive code, but this difference narrows progressively at higher SNRs. The complexity of the decoder asymptotically decreases (with SNR) as 1/(number of states), providing a good tradeoff between computational burden and performance. The proposed decoder is also within 1.0 dB of other well-known suboptimal soft-out decoding techniques     

A versatile time-domain Reed-Solomon decoder

A versatile Reed-Solomon (RS) decoder structure based on the time-domain decoding algorithm (transform decoding without transforms) is developed. The algorithm is restructured, and a method is given to decode any RS code generated by any generator polynomial. The main advantage of the decoder structure is its versatility, that is, it can be programmed to decode any Reed-Solomon code defined in Galois field (GF) 2^m with a fixed symbol size m. This decoder can correct errors and erasures for any RS code, including shortened and singly extended codes. It is shown that the decoder has a very simple structure and can be used to design high-speed single-chip VLSI decoders. As an example, a gate-array-based programmable RS decoder is implemented on a single chip. This decoder chip can decode any RS code defined in GF (2⁵) with any code word length and any number of information symbols. The decoder chip is fabricated using low-power 1.5-μ, two-layer-metal, HCMOS technology     

Decreasing energy consumption in address decoders by means of selective precharge schemes

This paper presents and evaluates three novel memory decoder designs which reduce energy consumption and delay by using selective precharging. These three designs, the AND-NOR, Sense-Amp, and the AND decoder, range in selectivity and select-line swing; these schemes charge and discharge fewer select-lines. This in turn consumes less energy than nonselective address decoders which charge and discharge all select-lines each cycle. These three decoding schemes are comprehensively simulated and compared to the conventional nonselective NOR decoder using 65 nm CMOS technology. Energy, delay, and area calculations are provided for all four 4-to-16 decoders under analysis. The most selective AND decoder performs best and dissipates between 61% and 99% less (73% less on average) and the selective Sense-Amp decoder performs only slightly worse by dissipating between 58% and 75% less (66% less on average) energy than dissipated by the NOR decoder. The AND-NOR decoder dissipates between 15% less and 20% more (6% more on average) energy than dissipated by the NOR decoder. In addition, the AND decoder is 7.5% and the Sense-Amp decoder is 5.0% faster than the NOR decoder, however, the AND-NOR decoder is 1.7% slower than the NOR decoder.