基于微谐振器的圆片级真空封装真空度测试技术

针对微电子机械系统(MEMS)圆片级封装腔体体积小、传统的真空封装测试方法适用性差的情况,研制了一种用于表征圆片级真空封装真空度的器件——MEMS微谐振器。利用此谐振器不仅可以表征圆片级真空封装真空度,也可用于圆片级真空封装漏率的测试。采用MEMS体硅工艺和共晶圆片键合技术实现了微谐振器的圆片级真空封装,利用微谐振器阻尼特性建立了谐振器品质因数与真空度的对应关系,通过设计的激励电路实现了微谐振器品质因数的在片测试,对不同键合腔体真空度下封装的MEMS微谐振器进行测试,测试结果显示该微谐振器在高真空度0.1～8 Pa范围内品质因数与真空度有很好的对应关系。     

圆片级封装用玻璃通孔晶片的减薄工艺北大核心

对圆片级封装用玻璃通孔（TGV）晶片的减薄加工工艺进行了研究并最终确定出工艺路线。该减薄加工工艺主要包括机械研磨及化学机械抛光（CMP）过程。通过机械研磨,玻璃通孔晶片的残余玻璃层及硅层得到有效去除,整个晶片的平整度显著提高,用平面度测量仪测试该晶片研磨后的翘曲度与总厚度变化（TTV）值分别为7.149μm与3.706μm。CMP过程使得TGV晶片的表面粗糙度大幅度降低,经白光干涉仪测试抛光后TGV晶片的表面粗糙度为4.275 nm。通过该减薄工艺加工的TGV晶片能够较好满足圆片级封装时的气密性要求。     

基于扇出型封装塑封材料性能的表征研究

扇出型封装在塑封过程中会出现芯片偏移及翘曲等缺陷,详细了解环氧塑封材料(EMC)的特性能够准确预测封装材料、结构、塑封工艺对塑封效果的影响。针对用于扇出型封装的EMC材料采用动态机械分析仪、差示扫描量热仪、流变仪测试其动态力学性能、固化动力学性能、流变学性能和热容,并建立可用于有限元分析的材料特性数学模型。结果表明,EMC在150℃等温固化60 min后具有最少残余固化;100℃环境下黏度随温度增加速率最快;时温等效原理可预测实验频率以外的力学行为。模型曲线与实验数据的拟合优度均大于0.982,材料表征模型满足准确性与适用性的要求。     

Applied NokotaTM电化学沉积系统助力先进芯片封装

应用材料公司日前宣布,面向晶圆级封装(WLP)产业推出Applied Nokota?电化学沉积(Electrochemical Deposition, ECD)系统,凭借优秀的电化学沉积性能、可靠性、晶圆保护能力、可扩展性,以及生产力,提供先进封装技术.在该系统的助力下,芯片制造商、外包装配和测试(OSAT)企业将可通过低成本、高效率的方式使用不同的晶圆级封装工艺,包括凸块/柱状、扇出、硅通孔(TSV)等等,满足日益增多的移动和高性能计算应用需求.     

松下电工开发通过晶圆级接合4层封装LED

松下电工成功开发出通过晶圆级接合,将封装有LED的晶圆和配备有光传感器的晶圆,合计4枚晶圆进行集成封装。该公司为了显示其晶圆级封装（WLP）的技术实力,在“第20届微机械／MEMS展”     

超薄型圆片级芯片尺寸封装技术

ShellCase公司的圆片级封装技术工艺,采用商用半导体圆片加工设备,把芯片进行封装并包封到分离的腔体中后仍为圆片形式。圆片级芯片尺寸封装(WL-CSP)工艺是在固态芯片尺寸玻璃外壳中装入芯片。玻璃包封防止了硅片的外露,并确保了良好的机械性能及环境保护功能。凸点下面专用的聚合物顺从层提供了板级可靠性。把凸点置于单个接触焊盘上,并进行回流焊,圆片分离形成封装器件成品。WL-CSP封装完全符合JEDEC和SMT标准。这样的芯片规模封装(CSP),其测量厚度为300μm-700μm,这是各种尺寸敏感型电子产品使用的关键因素。     

晶圆级树脂基低成本W波段封装天线微系统

面向W波段探测与通信系统的小型化、低成本应用需求,本文采用晶圆级树脂基扇出型封装工艺,通过对有源封装天线集成架构、互连传输结构和天线阵列进行设计与仿真,设计了一款工作频率为94 GHz的封装天线微系统。该封装天线微系统集成了4×4磁电偶极子阵列天线和16通道幅相多功能射频芯片。通过Ansys HFSS全波仿真,系统波束扫描范围在E面≥±30°,H面≥±40°,在7.1 mm×8.3 mm×1.2 mm封装尺寸内实现了封装天线等效全向辐射功率≥39.1 dBm。该封装天线微系统具备规模扩展能力,可广泛应用于探测、通信以及安检等领域。     

用于IC封装的光刻设备

光刻是圆片级封装的一种最重要的工艺,无论是焊盘分布、焊凸形成、密封或其它新出现的需求,晶圆上精确的成像区域对每一种工序来讲是最重要的。评述了一些圆片级封装的光刻系统及为什么某些专门的设备能很好地适于应用,会是接近式光刻机、步进投影光刻机还是一些替代设备在未来的几年内来满足这种需求?我们将探索这种可能性。     

圆片级封装技术

圆片级封装(Wafer-LevelPackaging,WLP)已成为先进封装技术的重要组成部分,圆片级封装能够为芯片封装带来批量加工的规模经济效益。在圆片规模上开始加工,结束于芯片规模的圆片级封装技术将在面型阵列倒装芯片的封装中得到日益广泛的应用。圆片级封装加工将成为业界前端和后端之间的高性能衔接桥梁。综述了圆片级封装的技术及其发展趋势。     

"魔法"激光划片-MAHOH

划片工艺概述划片工艺隶属于晶圆加工的封装部分,它不仅仅是芯片封装的核心关键工序之一,而且是从圆片级的加工(即加工工艺针对整片晶圆,晶圆整片被同时加工)过渡为芯片级加工(即加工工艺针对单个芯片)的地标性工序。从功能上来看,划片工艺通过切割圆片上预留的切割划道(street),将众多的芯片相互分离开,为后续正式的芯片封装做好最后一道准备。划片工艺的发展历程在最早期,人们通过划片机(Scriber)来进行芯片的切割分离,其过程类似于今天的手工划玻璃,用金刚刀在被切割晶圆的表面刻上一道划痕,然后再通过裂片工艺使晶圆沿划痕分割成单个芯…     

Warpage simulation and experimental verification for 320 mm × 320 mm panel level fan-out packaging based on die-first process

Warpage for 320 mm × 320 mm panel level fan-out packaging based on die-first process was investigated by both simulation and experimental approaches. In the present paper, a simple and efficient FEA (Finite Element Analysis) method based on shell element was introduced. Finite element models were built by using the software of Ansys products to predict and analysis the warpage for feasibility of large panel fan-out packaging technology in aspect of material, package geometries, package size, process conditions and metal density. In order to verify the accuracy and the precision of the simulation method, test vehicle with dies was fabricated by using low cost ‘die first (face down)’ fan-out technology. Warpage of the test vehicle was measured by using Shadow Moiré method. The simulated warpage result and the experimental one exhibit good consistency.     

Warpage simulation for the reconstituted wafer used in fan-out wafer level packaging

Fan-out packaging technology involves processing redistribution interconnects on reconstituted wafer, which takes the form of an array of silicon dies embedded in epoxy molding compound (EMC). Yields of the redistribution interconnect processes are significantly affected by the warpage of the reconstituted wafer. The warpage can be attributed to the crosslinking reaction and viscoelastic relaxation of the EMC, and to the thermal expansion mismatch between dissimilar materials during the reconstitution thermal processes. In this study, the coupled chemical-thermomechanical deformation mechanism of a commercial EMC was characterized and incorporated in a finite element model for considering the warpage evolution during the reconstitution thermal processes. Results of the analyses indicate that the warpage is strongly influenced by the volume percentage of Si in the reconstituted wafer and the viscoelastic relaxation of the EMC. On the other hand, contribution from the chemical shrinkage of the commercial EMC on warpage is insignificant. As such, evaluations based on the comprehensive chemical-thermomechanical model considering the full process history can be approximated by the estimations from a simplified viscoelastic warpage model considering only the thermal excursion.     

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage

Polyimide is widely used as the dielectric material in wafer level packaging. One potential problem with its application is the warpage and stress generated in the curing process. This paper investigated the material properties of polyimide and its influence on the wafer warpage. The viscoelastic properties of polyimide film were measured and a mathematical model of the properties was developed. Finite element analysis of the wafer warpage was performed and this indicates that the viscoelastic material model gave the best prediction. To better understand the causation of the warpage, curvature evolution of the polyimide-coated silicon wafer during its curing process was measured by a multi-beam optical sensor system. It was found that the warpage was mainly induced by the coefficient of thermal expansion mismatch and that the cure shrinkage of polyimide had little effect. Additionally, the effect of the cooling rate on the wafer warpage was also studied. Both simulation and experiment results showed that a slower cooling rate in the temperature range around the glass transition temperature (T _g) of polyimide will help to reduce the final wafer warpage.     

基于BCB键合的MEMS加速度计圆片级封装工艺

对基于BCB的圆片级封装工艺进行了研究,该工艺代表了MEMS加速度计传感器封装的发展趋势,是MEMS加速度计产业化的关键。选用3000系列BCB材料进行MENS传感器的粘结键合工艺试验,解决了圆片级封装问题,在低温250℃和适当压力辅助下≤2．5bar（1bar=100kPa）实现了加速度计的圆片级封装,并对相关的旋涂、键合、气氛、压力等诸多工艺参数进行了优化。     

晶圆级多层堆叠技术

随着5G和人工智能等新型基础设施建设的不断推进,单纯通过缩小工艺尺寸、增加单芯片面积等方式带来的系统功能和性能提升已难以适应未来发展的需求。晶圆级多层堆叠技术作为能够突破单层芯片限制的先进集成技术成为实现系统性能、带宽和功耗等方面指标提升的重要备选方案之一。对目前已有的晶圆级多层堆叠技术及其封装过程进行了详细介绍;并对封装过程中的两项关键工艺,硅通孔工艺和晶圆键合与解键合工艺进行了分析;结合实际封装工艺对晶圆级多层堆叠过程中的可靠性管理进行了论述。在集成电路由二维展开至三维的发展过程中,晶圆级多层堆叠技术将起到至关重要的作用。     

Wafer-level hermetic MEMS packaging by anodic bonding and its reliability issues

This paper reviews wafer-level hermetic packaging technology using anodic bonding from several reliability points of view. First, reliability risk factors of high temperature, high voltage and electrochemical O₂ generation during anodic bonding are discussed. Next, electrical interconnections through a hermetic package, i.e. electrical feedthrough, is discussed. The reliability of both hermetic sealing and electrical feedthrough must be simultaneously satisfied. In the last part of this paper, a new wafer-level MEMS packaging material, anodically-bondable low temperature cofired ceramic (LTCC) wafer, is introduced, and its reliability data on hermetic sealing, electrical interconnection and flip-chip mounting on a printed circuit board (PCB) are described.     

Foreword Wafer-Level Packaging

The four papers in this special section focus on wafer-level packaging. The selected papers cover the state-of-the-art and future development trends for wafer level chip scale packages (WLCSPs) by the leading institutes and industries operating in this field.