基于RRAM双交叉阵列结构的三值存内逻辑电路设计

在RRAM交叉阵列结构中实现逻辑运算可以较好地解决传统冯诺依曼架构中的存储墙问题.三值逻辑相比于传统的二值逻辑,具有更少的逻辑操作数目和更快的运算速度.文中提出了一种基于RRAM双交叉阵列结构的三值存内逻辑电路设计,其中三值逻辑电路的输入与输出均通过多值RRAM的阻值表示.该结构支持两种三值逻辑门和一种二值逻辑门以提升...     

基于忆阻器-CMOS晶体管的逻辑电路及其应用

针对传统组合逻辑电路存在的硬件资源利用率低和功耗高等问题,提出了一种基于忆阻器和CMOS晶体管的存算一体化组合逻辑电路设计方案。利用忆阻器存算一体、结构简单、与CMOS器件兼容等特性,减少了电路元器件数量。首先利用忆阻器的非易失性和阻变特性,设计忆阻与门、或门,结合CMOS晶体管实现与非门、或非门;然后,利用器件存算一体特性,提出了4R2T结构的异或门及同或门电路;最后,基于忆阻逻辑完备集设计了乘法器电路和图像加密电路,并采用LTspice验证电路功能正确性。结果表明,相比传统电路,所设计的乘法器电路元器件数量减少了50%,具有低功耗特性;所设计的图像加密电路具有良好的加密和解密效果,提升了运算效率。     

16×16位高速低功耗并行乘法器的实现

基于0.6μm双阱CMOS工艺模型,实现了一种高速低功耗16×16位并行乘法器。采用传输管逻辑设计电路结构,获得了低功耗的电路性能。采用改进的低功耗、快速Booth编码电路结构和4-2压缩器电路结构,它在2.5V工作电压下,运算时间达到7.18ns,平均功耗(100MHz)为9.45mW。     

基于阻变存储器的物理不可克隆函数设计

物理不可克隆函数(PUF)将集成电路制造过程中产生的工艺变化作为一种安全原语,已被广泛应用于硬件安全领域,特别是身份认证和密钥存储。提出了一种基于阻变存储器(RRAM)阵列的PUF优化设计,采用2T2R差分存储结构,并利用阵列中RRAM单元的阻值变化产生PUF的随机性,以实现更高安全级别所需的大量激励-响应对(CRP)。RRAM PUF的存储单元基于28 nm工艺实现,其面积仅为0.125μm²,相比传统PUF存储单元面积开销减小,在入侵和侧信道攻击方面具有更好的鲁棒性。实验数据表明,RRAM PUF唯一性达到了约49.78%,片内汉明距离为0%,一致性良好,具有较好的随机性。     

基于QCA的五输入Majority门设计及应用

Majority门作为多数逻辑电路的基本逻辑单元,其性能直接影响整体电路的质量.使用量子元胞自动机（QCA）设计Majority门具有结构简单的优点.本文提出了一种三层电路实现五输入Majority门的设计,并以此设计了全加器,进一步应用于多位加法器和乘法器中,与已发表的电路设计比较表明,其版图使用面积和元胞数有明显的减少,加法器元胞数和面积改进最高可达43%和87.2%,乘法器元胞数和面积改进最高可达48.2%和100%.     

一种结构新颖的流水线Booth乘法器设计

在对传统Booth乘法器研究的基础上,介绍了一种结构新颖的流水线型布什(Booth)乘法器。使用基-4 Booth编码、华莱士树(Wallace Tree)压缩结构、64位Kogge-Stone前缀加法器实现,并在分段实现的64位Kogge-Stone前缀加法器中插入4级流水线寄存器,实现32 t×32 bit无符号和有符号数快速乘法。用硬件描述语言设计该乘法器,使用现场可编程门阵列(Field Programmable Gate Array,FPGA)进行验证,并采用SMIC 0.18 μm CMOS标准单元工艺对该乘法器进行综合。综合结果表明,电路的关键路径延时为3.6 ns,芯片面积＜0.134 mm,功耗＜32.69 mW。     

基于矩阵编码的量子可逆逻辑电路进化设计方法

 本文研究基于遗传算法的量子可逆逻辑电路综合技术,能实现可逆逻辑电路功能、量子门数、垃圾位数和量子代价的多目标优化设计.建立了量子可逆逻辑电路综合数学模型,采用了量子可逆逻辑电路矩阵编码方案,设计了量子可逆逻辑电路进化操作算子,给出了量子可逆逻辑电路多目标进化设计算法.以8位量子可逆乘法器为设计实例,实验结果证明了所提出的量子可逆逻辑电路多目标进化设计方法是正确有效的.     

一种基于RRAM和表决器逻辑的新型乘法器

计算机系统快速发展,逐步进入大内存系统时代。但存储瓶颈的问题严重制约着计算机系统的进一步发展。结合RRAM这种非易失性存储器,设计了一种可以实现存储与计算一体化的逻辑运算架构。首次利用多数表决器逻辑实现了一种新型的全加器和乘法器,并给出了一种新型的逻辑运算单元架构。试验结果表明,该多数表决器逻辑实现全加器仅需4个步骤、3个单元,实现乘法器仅需24个步骤、42个单元,远远低于目前其他逻辑所需的步骤数和单元数。     

多元逻辑12位×12位超高速乘法器

本文以多元逻辑电路(DYL)中的线性与或门为“细胞,构思了体现这种基本门逻辑结构特长的高速数码乘法器结构方案,获得了比目前国际上商品化的高速乘法器更高的运算速度.实验设计制作的 12位× 12位乘法器实测结果表明:最大乘法时间在10ns左右,并能直接插入TTL电路系统使用. 文中分析了DYL线性与或门在二值逻辑系统中的逻辑结构、电路结构特点,提出了用这种基本门构成高速组合逻辑电路的综合方法,并讨论了实现这种基本门阵列高速的关键.     

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计.该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法.还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tilebased FPGA芯片设计所加的约束.该乘法器可以配置成同步或异步模式,也町以配置成带流水线的模式以满足高频操作.该设计很容易扩展成不同的输入和输出位宽.同时提出了一种新的超前进位加法器电路来产生最后的结果.采用了传输门逻辑来实现整个乘法器.乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns.全部使用2级的流水线时,时钟周期可以达到2.5ns.这比商用乘法器快29.1%,比其他乘法器快17.5%.与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.     

New domino logic precharged by clock and data

A clock-and-data precharged dynamic (CDPD) circuit technique in CMOS is presented. It gives a fast one-clock-cycle decision to multilevel logic and has small clock loads, low peak current, small area and low power-delay product. The technique is highly flexible in logic design. For the given example, a 324 bit binary-lookahead-carry chain, the speed improvement can be as high as 40-50% compared to the static circuit and 30% to the normal domino circuit arrangements while the area is reduced by 15-30%.<>     

Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

This paper proposes an 8?×?8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8?×?8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35?μm standard CMOS process.     

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.     

DB-driver: a low power CMOS bootstrapped differential cross-coupled driver

This paper for the first time reports the design of a high speed and low power differential cross-coupled bootstrapped CMOS driver circuit. The circuit design style, based on the proposed differential cross-coupled bootstrapped driver achieves high performance low core area, and fast full-swing operation, even in spite of the fact that the magnitude of the threshold voltage of the CMOS devices cannot be scaled down with the scaling of the power supply voltage. The proposed driver is implemented on 0.13?µm CMOS technology with a power supply of 1.2?V. It is 34% faster and provides 8% less core area when compared to a base-line circuit using an indirect bootstrap technique. In addition, the proposed driver reduces the power consumption by 35%. The superior performance of the proposed circuit over the other differential cross-coupled bootstrapped CMOS driver circuit, for the applications that require high performance, has been verified with post-layout simulation.     

Performance of CMOS differential circuits

Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are performed in terms of area, number of transistors, and propagation delay. Results indicate that in general, dynamic differential circuit techniques are faster than their conventional static counterparts. Further improvement in circuit performance can be achieved by choosing an appropriate differential structure to match logic structure being implemented. Second, even though the circuit techniques such as differential split-level perform better, they may not be widely accepted mainly because of the increase in circuit complexity and cost. Lastly, the self-timed dynamic differential circuit techniques yield considerable improvement in speed without having the problems of charge distribution or race conditions typically associated with the conventional single-ended domino circuit technique     

Skewed CMOS: noise-tolerant high-performance low-power static circuit family

In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.     

An algorithmic and novel design of a leading zero detector circuit:comparison with logic synthesis

A novel way of implementing the leading zero detector (LZD) circuit is presented. The implementation is based on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. We designed a 32 and 64 bit leading zero detector circuit in CMOS and ECL technology. The CMOS version was designed using both: logic synthesis and an algorithmic approach. The algorithmic implementation is compared with the results obtained using modern logic synthesis tools in the same 0.6 μm CMOS technology. The implementation based on an algorithmic approach showed an advantage compared to the results produced by the logic synthesis. ECL implementation of the 64 bit LZD circuit was simulated to perform in under 200 ps for nominal speed     

新型阻变存储器内的电压解决方案

相对于现在流行的FLASH型存储器,新型阻变存储器(resistive-RAM,RRAM)有很多优势,比如较高的存储密度和较快的读写速度。而针对RRAM的读写操作特性,提出了一种适用于新型阻变存储器的提供操作电压的电路。该方案解决了新型存储器需要外部提供高于电源电压的操作电压的问题,使得阻变存储器能应用于嵌入式设备。同时,对工艺波动和温度波动进行补偿,从而降低了阻变存储器的读写操作在较差的工艺和温度环境下的失败概率,具有很强的实际应用意义。该设计采用0.13μm标准CMOS 6层金属工艺在中芯国际(SMIC)流片实现,测试结果表明,采用此电路的RRAM能正确地进行数据编程和擦除等操作,测试结果达到设计要求。     

A multisampling time-domain CMOS imager with synchronous readout circuit

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The proposed multisampling architecture requires only a single bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The goal is to obtain a time-domain imager with high dynamic range that requires lower number of transistors per pixel in order to achieve higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operate in video mode having 10 bit pixel data resolution. Also, we present analysis of the impact of comparator offset voltage on the fixed pattern noise. The architecture was implemented in an imager prototype with 32 × 32 pixel array fabricated in AMS CMOS 0.35 μm and was characterized for sensitivity, noise and color response. The pixel size is 30 μm × 26 μm and it is composed of an n+/psub photodiode, a comparator and a D flip-flop with a 16% fill-factor.     

Novel low-voltage low-power full-swing BiCMOS circuits

A novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit technique; simple buffers, logic gates, and master-slave latches. Their performance, regarding speed, area, and power, was compared to that of CMOS for different technologies and supply voltages. Both device and circuit simulations were used. A design procedure for the feedback circuit and the effects of scaling on that procedure were studied and reported