多频道通信程控频率合成器

本文以大规模锁相环集成电路为中心,提出了一种可程控的频率合成技术。探索了多频道无线通信频率切换的方法,并给出了电路设计参数,图表以及微机接口的硬件和软件流程。有效地解决了多频道通讯中的程控频道切换的问题。     

具有多环贴片单元的多频段频率选择面

本文对具有理想导电多环贴片单元的多频段率选择面进行了理论讨论和实验验证，发现窄环逼近法对于环宽少于０．２５λ的环是有效的，λ是频选面谐振频率的波长。一种单屏双环频率选择面证实了：（１）一种低通频选面，其Ｋａ波段信号反射，而Ｓ，Ｘ和Ｋｕ波段信号通过；（２）三频段系统，其Ｘ波段信号反射，而Ｓ和Ｋｕ波段信号传输，此外，利用将上述两个单屏串联起来的办法，研制了一种非相似双环单元的双屏四频段频率选择面。测量     

多频道电视播出技术及常见播出故障

为了提高多频道电视播出质量,本文深入探究了多频道电视播出的常见故障,介绍了多频道电视播出技术的表现模式,讨论了多频道电视硬盘播出设备问题,包括磁盘反复读写故障、电源安全故障、检测系统故障、硬盘强制退出故障,针对故障问题提出了针对性的处理对策。同时为提升多频道电视播出图像质量,提出了定期保养系统、优化计算机管控系统、机房信息发射管理等举措,全方位保障多频道电视播出质量。     

MELEXIS推出300MHz～930 MHz多频道接收器芯片

MLX71122是新型多频道RF接收器芯片系列的首款芯片。该新型车用级芯片是专门为不需授权的工业、科学与医学(ISM)频段和短距离装置(SRD)频段应用而设计的。所有多频道、多波段和频率捷变式遥感测量系统都得益于该接收器的可编程所相环路(P L L)。它只需通过软件在欧洲863MHz～87     

多环谐振式微机械陀螺频率跟踪电路研究

由于多环谐振式微机械陀螺的谐振频率较高,传统的数字控制电路对陀螺幅点信号的频率跟踪难以同时兼顾精度和速度的要求。在传统半球陀螺数字控制电路的基础上,提出了一种适用于多环谐振式微机械陀螺仪的频率跟踪电路,并首次运用于多环谐振式微机械陀螺。该电路以高速A/D转换电路为基础,通过对幅点信号高速采样计算频率和相位信息,并通过CORDIC算法产生输出信号。测试结果显示,该电路使多环谐振式微机械陀螺幅点信号的频率跟踪精度达到了0.78Hz,频率跟踪时间小于40μs,使控制电路的性能得到了极大提升。     

WCDMA网络规划中频率使用分析

频率资源是任何移动通信系统必须考虑的首要资源,因此在WCDMA网络规划中,对于频率资源的分析和使用是必须综合考虑的。本文从我国第三代公众移动通信系统的频率规划出发,讨论了频道间隔及中心频率位置的确定、频率使用计划,并对3G无线接入系统与GSM／GPRS无线系统干扰分析。     

基于多环锁相宽带细步进频率合成器的设计

为了满足宽频段、细步进频率综合器的工程需求,对基于多环锁相的频率合成器进行了分析和研究。在对比传统单环锁相技术基础上,介绍了采用DDS+PLL多环技术实现宽带细步进频综,输出频段10~13 GHz,频率步进10 kHz,相位噪声达到-92 dBc/Hz@1 kHz,杂散抑制达到-68 dBc,满足实际工程应用需求。     

UHF调谐线路设计计算

UHF频段频率范围在300～3,000兆赫(分米波段).UHF电视频段下限在我国、美国、日本和欧洲等都是470兆赫,上限各异,一般接近1,000兆赫,电感导线的长度可与振荡波长相比拟.因此讨论UHF调谐回路从长线理论出发,对UHF调谐线路进行分析和讨论.并对UHF调谐线路进行计算,主要应用数字计算机语言BASIC,按照我国电视标准,国际上的频率划分范围,编写程序计算结果.打印过程分别打印36、48、56、68个频道(即国际上划分标准)计算数据,这对我国启用UHF频段可以提供设计试制参考资料. 频率范围:按13～36频道,频率470～702兆赫;13～48频道,频率470～798兆赫;13～56频道,频率470～862兆赫;13～20频道,频率470～958兆赫.     

多径衰落移动无线系统中的同频道干扰预测

同频道干扰是微蜂窝结构移动通信网所要考虑的一个核心问题，要想成功地对任何一种频率再用无线系统进行规划设计，就必须很好地了解并分析研究同频道干扰对系统性能的影响。本文对具有Ｎａｋａｇａｍｉ衰落和对数正态衰落的同频道干扰特性进行了理论分析，并提出了对微蜂窝多径衰落移动无线电系统中的同频道干扰及其影响进行预测的近似方法。     

增加一级下变频以多差转一个频道的试验

早期国产的一次变频的电视转播发射机,差频即输出频率没有固定中放,只能固定收转一个频道的电视节目,因此在其发射频道以外(至少相隔一个频道以上)则不能方便地选择接收几个频道的信号进行收转。这种差转机,具有灵敏度高、结构简单等优点,为了达到机动地增加一定的频道进行收转之目的,就要     

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance.     

基于ARM和nRF905的无线数据收发系统

为无线随动控制系统的数据传输所设计的无线数据收发系统,采用ARM LPC2148和nRF905构成,工作在433MHz的ISM频段,最远传输距离可达1000m,数据速率为50Kb/s,工作电压为3.3V,在发射功率为-10dBm时,电流消耗为11mA,低功耗模式时电流消耗仅为42μA。系统采用DSS＋PLL频率合成技术和GMSK调制,信道数最多可达170个,能够满足需要多信道工作的特殊场合使用。     

Blind Equalization with Differential Detection for Channels with ISI and Fading

Schemes which combine differential detection and blind equalization, to eliminate the need for phase recovery and training sequence, are studied. Decision feedback is also added in an attempt to equalize null and fading channels. Using Godard and Modified Constant Modulus Algorithms (MCMA) new systems are proposed by combining coherent and noncoherent detection with these two algorithms. For MCMA, as it can track the carrier, neither differential detection nor a PLL is required. Contrarily, Godard Algorithm needs either differential detection or a PLL to correct phase error. While the proposed system combining differential detection, blind equalization and decision feedback can indeed, in principle, equalize different channels, the robustness of the system is compromised.     

A CMOS frequency synthesizer with an injection-locked frequencydivider for a 5-GHz wireless LAN receiver

A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 μm CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -54 dBc     

对基于DLL和PLL的射频CMOS振荡器的相位抖动比较

通过对 PL L 和 DL L 相位抖动的比较 ,结合 DL L 倍频器的结构特点 ,得出了一个有用的公式 ,这个公式可以用于在 PL L 和 DL L 两种结构中选择出一个最佳方案 ,使得在使用 CMOS工艺实现频率合成器时能够得到最佳的功耗和相位抖动的折衷 .对于倍频系数很大的倍频器宜采用基于 PL L 的结构 ,这样可以消耗较少的功率 ;而对于较小的倍频系数的倍频器要采用基于 DL L 的结构 ,这样相位抖动特性将非常优良     

A CMOS serial link for fully duplexed data communication

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 μm CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns     

S 波段上下变频器的设计

本文设计了S波段上下变频器的设计,基于ADF4113芯片研制了频率合成器锁相源,中频AGC增益放大器,设计了S波段同轴腔滤波器。并对接收机双通道的幅频特性和相频特性以及通道平衡度进行了测试。给出测试结果,杂散抑制-70dBc(500MHz带内),相位噪声-80dBc/Hz@1kHz,50dB的AGC放大器动态范围,验证了该方案的可行性。     

一种GSM手机发射机数字模块的设计

设计了一种GSM射频芯片的锁相环式直接调制发射机的数字模块,完成了对基带数据的差分编码,高斯滤波,对信道码的处理,多级噪声整形,给锁相环提供分频比,并实现了对发射和接收信道的选择。通过Matlab建模仿真,完成对各个模块的结构设计,通过RTL级代码设计和编写相应的testbench进行功能验证,在Modelsim下进行仿真,实现了预定要求。在实践当中,通过了TSMC0.18μm的CMOS工艺,实现了CHRF06/GSM/E-GSMDCS/PCS射频芯片的发射数字部分的功能。     

Capacity of AM-PSK on partially coherent fading channels

This paper presents numerical capacity curves for two discrete complex channels: (1) a slow-fading Rayleigh channel with discrete carrier tracking by a phase-locked loop (PLL), where the PLL SNR is proportional to the fading amplitude squared, and (2) a fast-fading Rician channel with carrier phase estimation for the line-of-sight path only. Both channel models assume independent fading of successively received symbols. Capacity calculations are performed for equiprobable signaling with 8-ary and 16-ary amplitude-modulated phase-shift-keyed (AM-PSK) constellations. On the Rayleigh channel, the AM-PSK constellations give gains between 2 and 9 dB over PSK, at SNRs between 5 and 40 dB. For the Rician channel, AM-PSK gives a capacity gain over PSK of up to 0.75 bit at high SNR     

A low-jitter PLL clock generator for microprocessors with lockrange of 340-612 MHz

A fully integrated, phase-locked loop (PLL) clock generator/phase aligner for the POWER3 microprocessor has been designed using a 2.5-V, 0.40-μm digital CMOS6S process. The PLL design supports multiple integer and noninteger frequency multiplication factors for both the processor clock and an L2 cache clock. The fully differential delay-interpolating voltage-controlled oscillator (VCO) is tunable over a frequency range determined by programmable frequency limit settings, enhancing yield and application flexibility. PLL lock range for the maximum VCO frequency range settings is 340-612 MHz. The charge-pump current is programmable for additional control of the PLL loop dynamics. A differential on-chip loop filter with common-mode correction improves noise rejection. Cycle-cycle jitter measurements with the microprocessor actively executing instructions were 10.0 ps rms, 80 ps peak to peak (P-P) measured from the clock tree. Cycle-cycle jitter measured for the processor in a reset state with the clock tree active was 8.4 ps rms, 62 ps P-P. PLL area is 1040×640 μm². Power dissipation is <100 mW