Study and improvement of electrical performance of 130 nm Cu/CVD low k SiOCH interconnect related to via etch process

130 nm technology uses Cu/low k dielectrics integration for the back-end-of-line (BEOL) process. The motivation of this work was to assess and improve the electrical yields of dense via chains through the study of effects of via etch process splits. We also demonstrate successful wafer fabrication of two Cu-level interconnects with chemical vapor deposited (CVD) low k SiOCH material using dual damascene architecture processed on 200 mm wafers. As a result, we achieved excellent wafer level electrical yields for both dense via chains and metal bridging-continuity structures of the BEOL interconnections.     

Impact of barrier deposition process on electrical and reliability performance of Cu/CVD low k SiOCH metallization

Integration of Cu with low k dielectrics provided solution to reduce both resistance-capacitance time delay and parasitic capacitance of BEOL interconnections for 130 nm and beyond technology node. The motivation of this work is to study and improve electrical and reliability performance of two-level Cu/CVD low k SiOCH metallization from the results of diffusion barrier deposition schemes. Barrier deposition schemes are (a) high-density-plasma 250 Å Ta; (b) surface treatment of forming gas followed by high-density-plasma 250 Å Ta and (c) bi-layer of 100 Å Ta(N)/150 Å Ta. In this work, we demonstrated the superior and competency of high-density-plasma Ta deposition for Cu/CVD low k metallization and achieved excellent electrical and reliability results. Wafers fabricated with high-density-plasma Ta barrier scheme resulted in the best electrical yields, >90% for testing vehicles of dense via chains (via size=200 nm) and interspersed comb structures (width/space=200 nm/200 nm). Dielectric breakdown strength of the interspersed comb structures obtained at electric field of 0.3 MV/cm was ∼4 MV/cm.     

Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment

Copper interconnect electromigration performance was examined in various structures and three low-k materials (k = 2.65–3.6) using advanced BEOL technology. Strong current dependence effect on electromigration lifetime in three levels via terminated metal lines structure was shown. Moreover, different process approach will lead to different EM behavior and related failure mode. Multi-modality electromigration behavior of Cu dual damascene interconnects were studied. Both Superposition and Weak-Link models were used for statistical determination of lifetimes of each failure models (Statistical method). Results were correlated to the lifetimes of respective failure models physically identified according to resistance time evolution behaviors (Physical method). Good agreement was achieved. Various testing structures are designed to identify the EM failure modes. Extensive failure analysis was carried out to understand the failure phenomena of various test structures. The activation energies of failure modes were calculated. The weak links of interconnect system were also identified. A significant improvement of electromigration (EM) lifetime is achieved by modification of the pre-clean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation before cap-layer deposition and adhesion of Cu/cap interface were found to be critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration MTF and activation energy. Results of present study suggest that interface of Cu interconnects is the key factor for EM performance for advanced BEOL technology design rules.     

Advanced CD Control Technology for 65-nm Node Dual Damascene Process

This paper describes an advanced critical dimension (CD) control technology for a 65-nm node dual damascene process and beyond. A newly developed deposition enhanced shrink etching (DESE) process was introduced into both via and trench etching. This technology realizes not only dynamic via shrink ranging 40 nm but also accurate trench CD control by feedforward technology. Etching performance was investigated by electrical results of 65-nm Cu/low-k interconnects using porous chemical-vapor deposition SiOC. The 100% yields of 60-M via chains verified the DESE process robustness.     

Impact of substituting SiO2 ILD by low k materials into AlCu RIE metallization

The impact of introducing a low k dielectric for gap fill into standard process flow of AlCu RIE metallization with SiO₂ ILD is described. The low k material is a carbon-doped silicon oxide deposited by CVD. Standard oxide treatment is used for further processing of the material, i.e. CMP, contact etch, resist strip and contact clean. The CMP polish rate and the via hole profiles are investigated. The capacitive coupling is reduced by 15% compared to a standard HDP oxide gap fill.     

Prediction of interfacial adhesion strength of nanoscale Al/TiN films passed through patterned BEOL interconnects

The patterned layout arrangement of back-end of line (BEOL) is an important factor among reliability issues of advanced interconnects technology. BEOL determines the likelihood of interfacial fracture when adhesion between dielectric materials and conductive metals becomes poor, especially when ultra low-k dielectric is introduced into the process of semiconductor devices. Interfacial delamination of dissimilar thin films comprising multi-level interconnects increases under external loading or thermal cycling stress during device manufacturing. An Al/TiN coating underneath an ordinary pattern of BEOL interconnects is selected in this research to estimate adhesive energy by using interfacial fracture theory based on finite element analysis. By adopting the framework of four-point bending test, the proposed simulated approach was validated before comparison of the adhesion of Al/TiN stacked coatings with experimental data. Analysis indicate that increasing dielectric thickness between interfaces of Al/TiN films and Al metal line patterns from 100 nm to 600 nm induces fracture growth with crack lengths exceeding 3.5 mm. In addition, the foregoing driving force of fracture could be achieved because of Young’s modulus of dielectrics, which are larger than 70 GPa.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

Effect of low k dielectrics on electromigration reliability for Cu interconnects

Multi-link statistical test structures were used to study the effect of low k dielectrics on EM reliability of Cu interconnects. Experiments were performed on dual-damascene Cu interconnects integrated with oxide, CVD low k, porous MSQ, and organic polymer ILD. The EM activation energy for Cu structures was found to be between 0.8 and 1.0 eV, indicating mass transport dominated by diffusion at the Cu/SiN_x cap-layer interface, independent of ILD. Compared with oxide, the decrease in lifetime and (jL)_c observed for low-k structures can be attributed to less dielectric confinement in the low k structures. An effective modulus B obtained by finite element analysis was used to account for the dielectric confinement effect on EM and found to correlate well with EM lifetime and the (jL)_c product of low-k interconnects.     

Intra-level voltage ramping-up to dielectric breakdown failure on Cu/porous low-k interconnections in 45 nm ULSI generation

The degradation of reliability for intra-level voltage-breakdown in the 45 nm generation node has become an increasingly important issue with the introduction of porous low-k dielectrics. The dominant failure mechanism for lower voltage ramping-up to dielectric breakdown and higher leakage current was that more electrons easily transported through the percolation path in intra-level porous low-k interconnections damaged from HF corrosion. An optimal ultraviolet curing process and a less NH₃ plasma pre-treatment on porous low-k dielectrics before the SiCN capping layer are developed to improve performance in both of these cases. The stiff configuration of the reconstruction of Si-O network structures and less HF corrosion is expected to have high tolerance to electrical failure. As a result, the proposed model of this failure facilitates the understanding of the reliability issue for Cu/porous low-k interconnections in back-end of line (BEOL) beyond 45 nm nodes.     

200-mm wafer-scale transfer of 0.18-/spl mu/m dual-damascene Cu/SiO/sub 2/ interconnection system to plastic substrates

We report a low-temperature (<200/spl deg/C) 200-mm wafer-scale transfer of a 0.18-/spl mu/m dual-damascene Cu/SiO/sub 2/ interconnection system to FR-4 plastic substrates using adhesive bonding. We demonstrate removal of the silicon bulk layer to leave behind a flexible 3-/spl mu/m-thick Si back-end-of-line (BEOL) circuit on a 0.1-mm-thick FR-4 wafer. The mechanical and electrical integrity of the thin Si BEOL circuit on FR-4 are confirmed by focused ion beam scanning electron microscope microscopy and current-voltage characterization on a variety of test structures, which include serpentine, via chain and Kelvin test structures on different locations on the wafer. This process will pave the path to allow integration of high-performance submicrometer Si electronics on plastic substrates.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

Anisotropic deposition of copper by H-assisted plasma chemical vapor deposition

In order to fill small via-holes and trenches for ultralarge scale integration (ULSI) interconnects, we propose an anisotropic chemical vapor deposition (CVD) method by which Cu is deposited at a high rate at the bottom of a trench compared to that at its side wall. The ion irradiation is the key to realize the anisotropic CVD. The anisotropy, which is a ratio of deposition rate at the bottom of a trench to that at its side wall, tends to increase with energy as well as flux of ions (H₃⁺ is the predominant ion) impinging on the substrate surface, while it does not depend on H flux. We demonstrate promising anisotropic filling of trenches by the anisotropic CVD method.     

Bottom‐Up Engineering of Subnanometer Copper Diffusion Barriers Using NH2‐Derived Self‐Assembled Monolayers

A 3‐aminopropyltrimethoxysilane‐derived self‐assembled monolayer (NH₂SAM) is investigated as a barrier against copper diffusion for application in back‐end‐of‐line (BEOL) technology. The essential characteristics studied include thermal stability to BEOL processing, inhibition of copper diffusion, and adhesion to both the underlying SiO₂ dielectric substrate and the Cu over‐layer. Time‐of‐flight secondary ion mass spectrometry and X‐ray spectroscopy (XPS) analysis reveal that the copper over‐layer closes at 1–2‐nm thickness, comparable with the 1.3‐nm closure of state‐of‐the‐art Ta/TaN Cu diffusion barriers. That the NH₂SAM remains intact upon Cu deposition and subsequent annealing is unambiguously revealed by energy‐filtered transmission electron microscopy supported by XPS. The SAM forms a well‐defined carbon‐rich interface with the Cu over‐layer and electron energy loss spectroscopy shows no evidence of Cu penetration into the SAM. Interestingly, the adhesion of the Cu/NH₂SAM/SiO₂ system increases with annealing temperature up to 7.2 J m^?2 at 400 °C, comparable to Ta/TaN (7.5 J m^?2 at room temperature). The corresponding fracture analysis shows that when failure does occur it is located at the Cu/SAM interface. Overall, these results demonstrate that NH₂SAM is a suitable candidate for subnanometer‐scale diffusion barrier application in a selective coating for copper advanced interconnects.     

32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k = 2.3

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low-k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.     

Facing the challenge of designing for Cu/low-k reliability

With the decrease of the feature size to 90 nm and lower new materials are introduced in the waferfabs. Copper replaced aluminium and low-k dielectrics served as a better isolator. But this change has serious consequences for the structural integrity of the IC interconnects after processing and package manufacturing. Due to the fact that the new materials have substantially different thermo-mechanical properties, sufficient reliability performance for the IC package becomes a key factor. This paper presents solutions for the reliability problems faced due to the introduction of Cu/low-k as a consequence of the packaging processes. The packaging processes that significantly endanger the Cu/low-k integrity are probing, wire bonding, and moulding. Examples of the reliability issues are presented; these are deep probe marks, metal peel off, and/or pulled-off IC layers. To solve these issues, packaging process conditions and material properties are tuned to better fit with the Cu/low-k technology. Hopefully, the lessons learned and the newly developed state-of-the-art modelling and experimental techniques will enable the industry to release the lower node technologies such as CMOS065.     

Interconnects for nanoscale MOSFET technology: a review

In this paper,a review of Cu/low-k,carbon nanotube(CNT),graphene nanoribbon(GNR)and optical based interconnect technologies has been done,Interconnect models,challenges and solutions have also been discussed.Of all the four technologies,CNT interconnects satisfy most of the challenges and they are most suited for nanometer scale technologies,despite some minor drawbacks.It is concluded that beyond 32nm technology,a paradigm shift in the interconnect material is required as Cu/low-k interconnects are approaching fundamental limits.     

SiLK™ etch optimization and electrical characterization for 0.13 μm interconnects

This paper is focused on the optimization of reactive ion etching (RIE) process of low-k polymeric spin-on dielectric (SOD) material, SiLK™ (Trade mark of Dow Chemical, USA), for 0.13 μm Cu-low-k interconnects technology and subsequent electrical characterization of the metallization. Damascene metallization of SiLK™ film was integrated with dual hardmask scheme and “trench first” approach. Etch processes for single damascene metal trench and dual damascene via and metal2 trench structures were developed and evaluated. Effect of SiN and SiC films used as one of the hard mask layers and copper cap layers for single and dual damascene formation were also evaluated. The advantages of using SiC over SiN layer as one of the (bottom) dual hardmask layers were demonstrated through the results of electrical performance. Integration issues related to process development were analyzed and discussed. Electrical and reliability performance of testing vehicles associated to different etch criteria were studied. Electrical yield of >90% was obtained for the structures under study, which indicated the wide process margin. The consistency of processes was further demonstrated through the successful integration of eight metal layers with SiLK™ dielectric film.     

Characterization of various insulators for possible use as low-k dielectrics deposited at temperatures below 200 °C

The aim of this study was the testing of various low-k insulators deposited at temperatures below approximately 200 °C for use in copper interconnects. Various spin-on glasses (SOGs), purchased from Filmtronics Inc. and polymers such as the well-known poly(methyl methacrylate) (PMMA), the newly synthesized Poly(2,2,2 tri-fluoro-ethyl methacrylate) (PFEMA) and poly(dymethyl-siloxane) (PDMS) were tested. The above materials were compared with respect to their handling (application, curing, mechanical strength, patterning) and dielectric constant. It was shown that organic polymers containing C–F (PFEMA) and Si–O (PDMS) bonds present considerable advantages (related to the value of k and to handling) for use in Cu/low-k interconnects compared with usual SOGs cured at low temperatures.     

三维闪存中基于钨互连的空气隙结构的制备工艺

将空气隙应用于逻辑器件后段金属互连线中可以有效降低互连线间的寄生电容,提升电路信号传输速度,但制备过程仍具有一定的困难。基于三维闪存(3D NAND)中后段(BEOL)W的自对准双重图形化(SADP)工艺,利用湿法刻蚀的方法在W化学机械平坦化(CMP)之后去除SiO_2介质层,然后再利用化学气相淀积(CVD)法淀积一层台阶覆盖率较低的介质在金属互连线层内形成空气隙。采用空气隙结构代替原来的SiO_2介质层可降低约37.4%的寄生电容,且薄膜的台阶覆盖率会进一步降低电容。TCAD仿真和电性能测试结果表明,采用该方法制备的空气隙结构可降低互连延迟。     

Band diagram for low-k/Cu interconnects: The starting point for understanding back-end-of-line (BEOL) electrical reliability

The starting point for describing the electrostatic operation of any semiconductor device begins with a band diagram illustrating changes in the semiconductor Fermi level and the alignment of the valence and conduction bands with other interfacing semiconductors, insulating dielectrics and metal contacts. Such diagrams are essential for understanding the behavior and reliability of any semiconductor device. For metal interconnects, the band alignment between the metal conductor and the insulating intermetal and interlayer dielectric (ILD) is equally important. However, relatively few investigations have been made. In this regard, we have investigated the band alignment at the most common interfaces present in traditional single and dual damascene low-k/Cu interconnect structures. We specifically report combined X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy (REELS) measurements of the Schottky barrier present at the ILD and dielectric Cu capping layer (CCL) interfaces with the Ta(N) via/trench Cu diffusion barrier. We also report similar measurements of the valence and conduction band offsets present at the interface between a-SiN(C):H dielectric CCLs and low-k a-SiOC:H ILDs (porous and non-porous). The combined results point to metal interfaces with the CCL having the lowest interfacial barrier for electron transport. As trap and defect states in low-k dielectrics are also important to understanding low-k/Cu interconnect reliability, we additionally present combined electron paramagnetic resonance (EPR) and electrically detected magnetic resonance (EDMR) measurements to determine the chemical identity and energy level of some electrically active trap/defect states in low-k dielectrics. Combined with the photoemission derived band diagrams, the EPR/EDMR measurements point to mid-gap carbon and silicon dangling bond defects in the low-k ILD and CCL, respectively, playing a role in electronic transport in these materials. We show that in many cases the combined band and defect state diagrams can explain and predict some of the observed reliability issues reported for low-k/Cu interconnects.