Low‐Power Channel‐Adaptive Reconfigurable 4×4 QRM‐MLD MIMO Detector

This paper presents a low‐complexity channel‐adaptive reconfigurable QR‐decomposition and M‐algorithm‐based maximum likelihood detection (QRM‐MLD) multiple‐input and multiple‐output (MIMO) detector. Two novel design approaches for low‐power QRM‐MLD hardware are proposed in this work. First, an approximate survivor metric (ASM) generation technique is presented to achieve considerable computational complexity reduction with minor BER degradation. A reconfigurable QRM‐MLD MIMO detector (where the M‐value represents the number of survival branches in a stage) for dynamically adapting to time‐varying channels is also proposed in this work. The proposed reconfigurable QRM‐MLD MIMO detector is implemented using a Samsung 65 nm CMOS process. The experimental results show that our ASM‐based QRM‐MLD MIMO detector shows a maximum throughput of 288 Mbps with a normalized power efficiency of 10.18 Mbps/mW in the case of MIMO with 64‐QAM. Under time‐varying channel conditions, the proposed reconfigurable MIMO detector also achieves average power savings of up to 35% while maintaining a required BER performance.     

Low‐Complexity Massive MIMO Detectors Based on Richardson Method

In the uplink transmission of massive (or large‐scale) multi‐input multi‐output (MIMO) systems, large dimensional signal detection and its hardware design are challenging issues owing to the high computational complexity. In this paper, we propose low‐complexity hardware architectures of Richardson iterative method‐based massive MIMO detectors. We present two types of massive MIMO detectors, directly mapped (type1) and reformulated (type2) Richardson iterative methods. In the proposed Richardson method (type2), the matrix‐by‐matrix multiplications are reformulated to matrix‐vector multiplications, thus reducing the computational complexity from O(U²) to O(U). Both massive MIMO detectors are implemented using a 65 nm CMOS process and compared in terms of detection performance under different channel conditions (high‐mobility and flat fading channels). The hardware implementation results confirm that the proposed type1 Richardson method‐based detector demonstrates up to 50% power savings over the proposed type2 detector under a flat fading channel. The type2 detector indicates a 37% power savings compared to the type1 under a high‐mobility channel.     

A Low‐Complexity 128‐Point Mixed‐Radix FFT Processor for MB‐OFDM UWB Systems

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency‐division multiplexing ultra‐wideband systems. The proposed 128‐point FFT processor employs both a modified radix‐2⁴ algorithm and a radix‐2³ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure‐sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 µm CMOS technology with a supply voltage of 1.8 V. The hardware‐ efficient 128‐point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128‐point mixed‐radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128‐point FFT architectures.     

Low power and high speed multiplier design with row bypassing and parallel architecture

This paper presents a low power and high speed row bypassing multiplier. The primary power reductions are obtained by tuning off MOS components through multiplexers when the operands of multiplier are zero. Analysis of the conventional DSP applications shows that the average of zero input of operand in multiplier is 73.8 percent. Therefore, significant power consumption can be reduced by the proposed bypassing multiplier. The proposed multiplier adopts ripple-carry adder with fewer additional hardware components. In addition, the proposed bypassing architecture can enhance operating speed by the additional parallel architecture to shorten the delay time of the proposed multiplier. Both unsigned and signed operands of multiplier are developed. Post-layout simulations are performed with standard TSMC 0.18 μm CMOS technology and 1.8 V supply voltage by Cadence Spectre simulation tools. Simulation results show that the proposed design can reduce power consumption and operating speed compared to those of counterparts. For a 16×16 multiplier, the proposed design achieves 17 and 36 percent reduction in power consumption and delay, respectively, at the cost of 20 percent increase of chip area in comparison with those of conventional array multipliers. In addition, the proposed design achieves averages of 11 and 38 percent reduction in power consumption and delay with 46 percent less chip area in comparison with those counterparts for both unsigned and signed multipliers. The proposed design is suitable for low power and high speed arithmetic applications.     

Low-latency bit-parallel systolic multiplier

A bit-parallel systolic multiplier based on pair-wise grouping of the bit products is presented. The proposed scheme yields significantly lower latency compared to existing systolic multipliers, without increasing the circuit complexity. High throughput is achieved, limited by the delay of a gated full adder and a latch.<>     

New efficient bit-parallel polynomial basis multiplier for special pentanomials

We present a bit-parallel polynomial basis multiplier based on a new divide-and-conquer approach using squaring. In particular, we apply the proposed approach to special types of irreducible pentanomials called as types I and II pentanomials, and induce explicit formulae and complexities of the proposed multiplier for these types of pentanomials. As a result, the proposed multiplier for type I pentanomials has almost the same time complexity, but about 25% reduced space complexity compared with the best known results in the literature. For type II pentanomials, we obtain the multiplier which has the lowest time complexity and about 25% reduced space complexity than the best known polynomial basis multipliers.     

Low‐Complexity Multi‐size Cyclic‐Shifter for QC‐LDPC Codes

The decoding process of a quasi‐cyclic low‐density parity check code requires a unique type of rotator. These rotators, called multi‐size cyclic‐shifters (MSCSs), rotate input data with various sizes, where the size is the amount of data to be rotated. This paper proposes a low‐complexity MSCS structure for the case when the sizes have a nontrivial common divisor. By combining the strong points of two previous structures, the proposed structure achieves the smallest area. The experimental results show that the area reduction was more than 14.7% when the proposed structure was applied to IEEE 802.16e as an example.     

Tripartite modular multiplication

This paper presents a new modular multiplication algorithm that allows one to implement modular multiplications efficiently. It proposes a systematic approach for maximizing a level of parallelism when performing a modular multiplication. The proposed algorithm effectively integrates three different existing algorithms, a classical modular multiplication based on Barrett reduction, the modular multiplication with Montgomery reduction and the Karatsuba multiplication algorithms in order to reduce the computational complexity and increase the potential of parallel processing. The algorithm is suitable for both hardware implementations and software implementations in a multiprocessor environment. To show the effectiveness of the proposed algorithm, we implement several hardware modular multipliers and compare the area and performance results. We show that a modular multiplier using the proposed algorithm achieves a higher speed comparing to the modular multipliers based on the previously proposed algorithms.     

On‐Chip Bus Serialization Method for Low‐Power Communications

One of the critical issues in on‐chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low‐power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word‐to‐word and bit‐by‐bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG‐4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost‐effective when implemented as a hardware circuit since its algorithm is very simple.     

FPGA implementation of highly secure,hardware‐efficient QC‐LDPC code–based nonlinear cryptosystem for wireless sensor networks

This paper presents the design and implementation of an integrated architecture for embedding security into quasi‐cyclic (QC) low‐density parity‐check (LDPC) code–based cryptographic system through a nonlinear function of low hardware complexity. Instead of using standard S ‐boxes for implementation of nonlinear function, this paper considers a method on the basis of maximum length cellular automata (CA), so that enhanced security can be achieved with simple hardware structure. The proposed system adopts a lightweight random bit stream generator on the basis of linear feedback shift register (LFSR) for generating random error vectors, so that a large number of vectors with very good cryptographic properties can be made available with low hardware cost. Different permutation patterns generated for different message blocks help to provide good degrees of freedom for tuning security with reasonable key size. The hardware architecture for the proposed system is developed and validated through implementation on Xilinx Spartan 3S500E. Analytical and synthesis results show that the proposed scheme is lightweight and offers very high security through continuously changing parameters, thus making it highly suitable for resource‐constrained applications.     

Highly molecular systolic structures for denominator-separable 2-Drecursive filters

Two systolic realization structures for the implementation of 2-D denominator-separable recursive filters are presented. These structures possess a high degree of modularity and parallelism with low roundoff noise. The number of delays and multipliers is fewer than for similar realizations in the literature. The proposed structures are more suitable for special-purpose hardware and amenable to VLSI design     

Constant Number Serial Pipeline Multipliers

The pipeline form of the serial/parallel multiplier for constant numbers, which operates without insertion of zero words between successive data, is presented. The constant number is in Canonical Signed Digit (CSD) form and the other factor in two's complement form. The CSD form was chosen because it yields significant hardware reduction. Also, for the above data forms the Lyon's serial pipeline multiplier is examined. For these designs, a special algorithm for the multiplication of two's complement numbers with constant numbers in CSD representation was developed. The proposed serial pipeline multipliers are compared with the existing schemes from the point of hardware complexity.     

Hardware-efficient FIR filters with reduced adder step

A technique for reducing the hardware complexity of constant coefficient finite impulse response (FIR) digital filters, without increasing the number of adder steps in the multiplier block adders, is presented. The filter coefficients are adjusted so that the number of full adders in the hardware implementation of any coefficient is independent of the coefficient wordlength and the number of shifts between nonzero bits in the coefficient. Results show that the proposed technique achieves a significant reduction in both the multiplier block adders and the multiplier block full adders when compared to existing techniques.     

Outage Probability of Decode‐and‐Forward Relaying Systems with Efficient Partial Relay Selection in Nakagami Fading Channels

Recently, efficient partial relay selection (e‐PRS) was proposed as an enhanced version of PRS. In comparing e‐PRS, PRS, and the best relay selection (BRS), there is a tradeoff between complexity and performance; that is, the complexity for PRS, e‐PRS, and BRS is low to high, respectively, but vice versa for performance. In this paper, we study the outage probability for e‐PRS in decode‐and‐forward (DF) relaying systems over non‐identical Nakagami‐m fading channels, where the fading parameter m is an integer. In particular, we provide closed‐form expressions of the exact outage probability and asymptotic outage probability for e‐PRS in DF relaying systems. Numerical results show that e‐PRS achieves similar outage performance to that of BRS for a low or medium signal‐to‐noise ratio, a high fading parameter, a small number of relays, and a large difference between the average channel powers for the first and the second hops.     

LFSR multipliers over GF(2) defined by all-one polynomial

This paper presents two bit-serial modular multipliers based on the linear feedback shift register using an irreducible all one polynomial (AOP) over GF(2^m). First, a new multiplication algorithm and its architecture are proposed for the modular AB multiplication. Then a new algorithm and architecture for the modular AB² multiplication are derived based on the first multiplier. They have significantly smaller hardware complexity than the previous multipliers because of using the property of AOP. It simplifies the modular reduction compared with the case of using the generalized irreducible polynomial. Since the proposed multipliers have low hardware requirements and regular structures, they are suitable for VLSI implementation. The proposed multipliers can be used as the kernel architecture for the operations of exponentiation, inversion, and division.     

Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers

An embedded test pattern generator scheme for large-operand (unlimited bit length) multiplier and divider is presented by employing a simple digital circuit. This scheme is based on the generation of cyclic code polynomials from a characterized polynomials generator G(X) and incorporated with Modified-Booth algorithm. Due to the advantages of the former, the hardware complexity is simple, and moreover, the multiplier and divider can share the same hardware with a small change of control lines. Due to the advantages of latter's schemes, the numbers of sub/add operations are reduced to one half of the multiplicand for the result of final product. Therefore, the proposed pipelined multipliers permit very high throughput for arbitrary value of digit size. Only full adders/subtractors and shift registers are used in the proposed multiplier and divider hardware. The input data of the multiplier/divider can be processed in parallel or in pipelined without considering carry/borrow delays during the operations. The speed of computation has therefore been greatly improved by approximately a factor of 2. Since most parts of the components can be used for both the multiplier and divider, with full adders replaced by subtractors for switching from a multiplier to a divider, the structure is therefore tremendously reduced. In addition, these function units are involved with cyclic code generators, so that they can be used as a built-in self-test (BIST).     

Enhanced Omnidirectional Photovoltaic Performance of Solar Cells Using Multiple‐Discrete‐Layer Tailored‐ and Low‐Refractive Index Anti‐Reflection Coatings

An optimized four‐layer tailored‐ and low‐refractive index anti‐reflection (AR) coating on an inverted metamorphic (IMM) triple‐junction solar cell device is demonstrated. Due to an excellent refractive index matching with the ambient air by using tailored‐ and low‐refractive index nanoporous SiO₂ layers and owing to a multiple‐discrete‐layer design of the AR coating optimized by a genetic algorithm, such a four‐layer AR coating shows excellent broadband and omnidirectional AR characteristics and significantly enhances the omnidirectional photovoltaic performance of IMM solar cell devices. Comparing the photovoltaic performance of an IMM solar cell device with the four‐layer AR coating and an IMM solar cell with the conventional SiO₂/TiO₂ double layer AR coating, the four‐layer AR coating achieves an angle‐of‐incidence (AOI) averaged short‐circuit current density, J_SC, enhancement of 34.4%, whereas the conventional double layer AR coating only achieves an AOI‐averaged J_SC enhancement of 25.3%. The measured reflectance reduction and omnidirectional photovoltaic performance enhancement of the four‐layer AR coating are to our knowledge, the largest ever reported in the literature of solar cell devices.     

New Multiplier for a Double‐Base Number System Linked to a Flash ADC

The double‐base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog‐to‐digital converters or digital systems through a double‐base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.     

A novel architecture and a systematic graph-based optimization methodology for modulo multiplication

A novel hardware algorithm, a VLSI architecture, and an optimization methodology for residue multipliers are introduced in this paper. The proposed design approach identifies certain properties of the bit products that participate in the residue product computation and subsequently exploits them to reduce the complexity of the implementation. A set of introduced theorems is used to identify the particular properties. The introduced theorems are of significant practical importance because they allow the definition of a graph-based design methodology. In addition, a bit-product weight encoding scheme is investigated in a systematic way, and exploited in order to minimize the number of bit products processed in the proposed multiplier. Performance data reveal that the introduced architecture achieves area /spl times/ time complexity reduction of up to 55%, when compared to the most efficient previously reported design.