A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter

Exploiting specific properties of the algorithm, a high-throughput pipelined architecture is introduced to implement the H.264/AVC deblocking filter. The architecture was synthesized in 0.18 μm technology and the clock frequency and area are 400 MHz and 16.8 Kgates, respectively. Also, it is able to filter 217 and 55 Frames per second (Fps) for Full- and Ultra-HD videos, respectively. The introduced architecture outperforms similar ones in terms of frequency (1.8× up to 4×), throughput, (1.5× up to 3.8×), and Fps. Moreover, extensions to support different sample bit-depths and chroma formats are included. Also, experimental results for different FPGA families are offered.     

Shared hardware,high throughput implementation of 2D 4 × 4 and 8 × 8 integer transform for H.264/AVC high-profile coders

Two-dimensional discrete cosine transforms are used in the core transformations in all profiles of the H.264/Advanced video coding (AVC) standard. In this paper, implementing the resource sharing of high throughput 4 × 4 and 8 × 8 forward and inverse integer transforms for high definition H.264 is presented. It is shown that the 4 × 4 forward/inverse transform can be obtained from 8 × 8 forward/inverse transform using selective data input and data arrangement at intermediate stages. Fast 8 × 8 forward and inverse transform is implemented using matrix decomposition and matrix operation such as Kronecker product and direct sum. The proposed implementation does not require any transpose memory and has a dual clocked pipeline structure. Compared with existing designs, the gate count is reduced by 27.7% in the proposed design. The maximum operating frequency of the proposed system is approx. 1.3 GHz, while the throughput is 7 G and 18.7 G pixels/s for 4 × 4 and 8 × 8 forward integer transforms, respectively. The proposed design can be used for real time H.264/AVC high definition processing owing to its high throughput and low hardware cost.     

Blind image watermarking via exploitation of inter-block prediction and visibility threshold in DCT domain

In this paper, the backward-propagation neural network (BPNN) technique and just-noticeable difference (JND) model are incorporated into a block-wise discrete cosine transform (DCT)-based scheme to achieve effective blind image watermarking. To form a block structure in the DCT domain, we partition a host image into non-overlapped blocks of size 8 × 8 and then apply DCT to each block separately. By referring to certain DCT coefficients over a 3 × 3 grid of blocks, the BPNN can offer adequate predictions of designated coefficients inside the central block. The watermarking turns out to be a process of adjusting the relationship between the intended coefficients and their BPNN predictions subject to the JND. Experimental results show that the proposed scheme is able to withstand a variety of image processing attacks. Compared with two other schemes that also utilize inter-block correlations, the proposed one apparently exhibits superior robustness and imperceptibility under the same payload capacity.     

Hardware implementation and validation of the fast variable block size motion estimation architecture for H.264/AVC

Block matching motion estimation is the heart of video coding system. It leads to a high compression ratio, whereas it is time consuming and calculation intensive. Many fast search block matching motion estimation algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose an efficient hardware architecture of the fast line diamond parallel search (LDPS) algorithm with variable block size motion estimation (VBSME) for H.264/AVC video coding system. The design is described in VHDL language, synthesized to Altera Stratix III FPGA and to TSMC 0.18 μm standard-cells. The throughput of the hardware architecture reaches a processing rate up to 78 millions of pixels per second at 83.5 MHz frequency clock and uses only 28 kgates when mapped to standard-cells. Finally, a system on a programmable chip (SoPC) implementation and validation of the proposed design as an IP core is presented using the embedded video system.     

Wheel shaped modified fractal antenna realization for wireless communications

A compact, low profile circular fractal patch antenna with low latency, low cost, high speed and multiband is presented. With the help of CST Microwave Studio Suite TM the proposed structure has been designed and analyzed. The simulated results are fixed experimentally. The suggested antenna has dimension of 32 × 36 mm² (W × L) and operating from 2.93 GHz–9.53 GHz with VSWR ≤ 2. The aerial is assembled on FR-4 (ε_r = 4.4) substrate with a thickness of substrate 1.25 mm. Detailed parametric studies of the antennas have been carried out. This microstrip fed antenna is suitable for ultra wideband (UWB), S, C and part of the X band applications.     

A dual-loop shunt regulator using current-sensing feedback techniques

The dual-loop shunt regulator using current-sensing feedback techniques is proposed in this paper. This architecture adopts a voltage and current loops to increase the transient response of the proposed shunt regulator. The maximum output current of the proposed shunt regulator is 180 mA at a 1.8 V output. Moreover the architecture of the proposed shunt regulator can suppress the stray effect which is from power supply. The prototype of the proposed shunt regulator is fabricated by the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.35-μm CMOS 2P4M process. The active area is only 579×355 μm².     

Surface reconstructions on Sb-irradiated GaAs(0 0 1) formed by molecular beam epitaxy

Reconstructed surfaces on Sb-irradiated GaAs(0 0 1) formed by molecular beam epitaxy have been studied by in-situ scanning tunneling microscopy (STM). The reflection high-energy electron diffraction patterns showed (2×3) [or weak (4×3)] structure. The step density was about five times higher than that of GaAs(0 0 1)-c(4×4) surface. It was found that there were swinging dimer rows along to the [1 1¯ 0] direction, which seemed not to consist of a specified reconstruction. We proposed two (2×3)-structure models for these swinging dimers. By first-principles calculation, we found that the proposed models were stable and with energy difference was 0.17 eV, indicating the coexistence of the two structures. Moreover, we proposed three (4×3) reconstruction models based on these (2×3) models. The electron counting rule was applied for these models, indicating that there was an excessive amount of electrons. By two bias-alternative STM images, it was found that the many spots appear only in empty-state. These might be segregated Ga or Sb cluster and strongly relate to the excessive amount of electrons.     

A PAPR reduction technique using Hadamard transform combined with clipping and filtering based on DCT/IDCT for IM/DD optical OFDM systems

In Intensity Modulator/Direct Detection (IM/DD) optical OFDM systems, the high peak-to-power average ratio (PAPR) will cause signal impairments through the nonlinearity of modulator and fiber. In this paper, a joint PAPR reduction technique based on Hadamard transformation and clipping and filtering using DCT/IDCT transform has been proposed for mitigating the impairments in IM/DD optical OFDM system. We then experimentally evaluated the effect of PAPR reduction on the bit error rate (BER) performance and the results show the effectiveness of the proposed technique. At a bit error rate (BER) of 1 × 10⁻³, the receiver sensitivity of the proposed 2.5 Gb/s IM/DD optical OFDM system after 100-km standard single-mode fiber transmission has been improved by 0.8 dB, 1.3 dB and 3.1 dB for a launch power of 6.4 dBm, 8 dBm and 10 dBm respectively when compared with the classical system.     

Distortion free image-in-image communication with implementation in FPGA

The proliferation of the digitized media (audio, image and video) introduces a challenging problem for data transmission in the network environment. In this paper, a novel, simple and low cost algorithm that serves the purpose of distortion free covert image-in-image communication is proposed. Its very large scale integration (VLSI) implementation using field programmable gate array (FPGA) is also developed. A binary equivalent message signal is developed first from the combination of the auxiliary gray scale image information and the carrier gray scale image (original) using channel coding and spatial bi-phase modulation scheme. The auxiliary image information is then decoded from the distorted/distortion free version of the original image using binary message under certain noise constraint. Implementation of the proposed low cost algorithm can be speeded up significantly by hardware realization. The developed hardware design allows data transmission at the rate of 4.706 Mbits/s at 80 MHz clock frequency.     

Software-driven sensor networks for short-range shallow water applications

Most existing underwater networks target deep and long range oceanic environments, which has led to the design of power hungry and expensive underwater communication hardware. Because of prohibitive monetary and energy cost of currently over-engineered communication hardware, dense deployments of shallow water sensor networks remain an elusive goal. To enable dense shallow water networks, we propose a network architecture that builds on the success of terrestrial sensor motes and that relies on the coupling of software modems and widely available speakers and microphones in sensor motes to establish acoustic communication links. In this paper, we analytically and empirically explore the potential of this acoustic communication system for the underwater environment. Our experimental approach first profiles the hardware in water after waterproofing the components with elastic membranes. The medium profiling results expose the favorable frequencies of operation for the hardware, enabling us to design a software FSK modem. Subsequently, our experiments evaluate the data transfer capability of the underwater channel with 8-frequency FSK software modems. The experiments within a 17 × 8 m controlled underwater environment yield an error-free channel capacity of 24 bps, and they also demonstrate that the system supports date rates between 6 and 48 bps with adaptive fidelity.     

Wafer-level LED-SiP based mobile flash module and characterization

In this paper, we have developed and revealed the wafer-level LED system-in-packaging (WL-LED-SiP) design and process platform. This platform provided an LED system solution with high packaging density, high performance, high reliability and cost effectiveness. Camera phone flash module was adopted as a test vehicle for demonstrating LED-SiP platform technologies, including wafer-level (WL) process integration with micro electromechanical system (MEMS) reflector, cavity-based lithography and through silicon via (TSV) filling. Meanwhile, LED flash module performance, including correlated color temperature (CCT), color rendering index (CRI), light energy and distribution, was characterized. The delivered LED-SiP flash module showed wide-view angle design of 80° × 50° and light energy of 5.7 lx s @ 1/30 s. The volume of the module is 8 × 11 × 4 mm³.     

A high-bandwidth,high-precision,two-axis steering mirror with moving iron actuator

This paper focuses on the design, fabrication, assembly, and testing of high bandwidth two-axis mirror positioners for precision optical platforms, which we refer to as the Advanced Fast Steering Mirror (AFSM) and the small Advanced Fast Steering Mirror (sAFSM). These novel positioners consist of a mirror platform driven in two rotational axes by flux-steering electromagnetic actuators, and controlled via position feedback loops. The devices are designed for beam stabilization tasks in lithography, laser communication, lidar, and similar optical applications. We have experimentally demonstrated small-signal system bandwidth of 10 kHz using optical quad-cell feedback and a two-channel analog control architecture. The AFSM has a travel range of ±3.5 mrad, and a measured angular acceleration of 1 × 10⁵ rad/s².     

Corrugated SIW K band horn antenna

In the recent years, the strong demand for high performance, low cost and high gain antennas for telecommunication, surveillance, and imaging applications has rapidly grown at microwave and higher frequencies. High speed wireless links require modular, compact size and high directivity with low cross polarization antennas. To demonstrate the proposed concepts and design features, in this paper, a substrate integrated waveguide (SIW) feeding technique has been created having well behaved gain and suitable −10 dB bandwidth from 23.8 GHz to 25.7 GHz (roughly 2 GHz bandwidth), while the impedance bandwidth for VSWR < 2.5 is nearly 3 GHz. The simulated antenna attains 12.5 ± 1 dB gain over majority of K band with an occupied size of 82 mm × 40 mm × 2.54 mm and has roughly 95% radiation efficiency. The proposed antenna is an excellent candidate for integrated low cost K band and even higher frequency systems. The simulations are done by two full wave packages i.e. ANSYS HFSS and CST MWS that associated with finite element method (FEM) and finite difference time domain (FDTD), respectively. The results show good agreements between these two methods.     

Configurable memristive logic block for memristive-based FPGA architectures

This article proposes a Configurable Memristive Logic Block (CMLB) that comprises of novel memristive logic cells. The memristive logic cells are constructed from memristive D flip-flop, 6-bit non-volatile look-up table (NVLUT), and multiplexers. The memristive logic cells are interconnected using memristive switch matrix cells to form the CMLB. The CMLB is then used to construct a memristor-based FPGA architecture. The proposed CMLB shows a reduction of 8.6% of device area and 1.094 times lesser critical path delay against the SRAM-based FPGA architecture. Against similar CMOS-based circuits, the memristive D flip-flop provides switching speed of 1.08 times faster, the NVLUT reduces power consumption by 6.25 nW, and the memristive logic cells reduce device area by 60.416 µm². In this research work also, various memristor-based FPGA architectures found in the literature are compared against the SRAM-based FPGA architecture.     

Design,fabrication and measurement of triple band frequency reconfigurable antennas for portable wireless communications

In this paper two triple-band monopole antennas are proposed for portable wireless applications such as WiFi, WiMAX and WLAN. Two different geometrical structures are used for the radiating elements of these antennas, each printed on a low cost FR-4 substrate. Truncated metallic copper ground is used to attain optimum radiation pattern and better radiation efficiency. The frequency of the antennas is reconfigured using a lumped-element switch. The proposed antennas covers three frequency bands 2.45, 3.50 and 5.20 GHz depending upon the switching conditions. Both antennas works with an optimum gain (1.7–3.4 dB), bandwidth (6–35%), VSWR (<1.5) and radiation efficiency (85–90%). Due to its affordable size (1.6 × 35 × 53 mm³), the antennas can be used in modern and portable communication devices such as laptops, iPads and mobile phones. The prototype of the antennas are fabricated and the measurements and simulations are found in close agreement.     

Cost-effective and monitoring-active technique for TDM-passive optical networks

A reliable, detection-active and cost-effective method which employs the hello and heartbeat signals for branched node distinguishing to monitor fiber fault in any branch of distribution fibers of a time division multiplexing passive optical network (TDM-PON) is proposed. With this method, the material cost of building an optical network monitor system for a TDM-PON with 168 ONUs and the time of identifying a multiple branch faults is significantly reduced in a TDM-PON system of any scale. A fault location in a 1 × 32 TDM-PON system using this method to identify the fault branch is demonstrated.     

Improved pilot-aided optical carrier phase recovery using average processing for pilot phase estimation

We propose and numerically investigate an improved pilot-aided (PA) optical carrier phase recovery (CPR) method using average processing for pilot phase estimation in order to suppress the amplified spontaneous emission (ASE) noise in PA coherent transmission systems. Extensive simulations for 28 Gbuad QPSK systems are implemented. The performance of proposed PA-CPR with averaging is comprehensively investigated and compared with PA-CPR without averaging and Viterbi & Viterbi phase estimation (VVPE). Results show that, PA-CPR with averaging can significantly improve the performance of PA-CPR without averaging, and the best averaging length in the average operation is determined by trading off between ASE noise and laser phase noise (PN). By comparing the optical-signal-to-noise-ratio (OSNR) penalties at bit error rate (BER) of 1 × 10^?3 using PA-CPR without averaging, PA-CPR with averaging and VVPE, the advantage of PA-CPR with averaging is further confirmed. Quantitatively, the tolerable linewidth-symbol-duration products (Δf · T) at 1-dB OSNR penalty by using PA-CPR without averaging, VVPE, and PA-CPR with averaging are 6 × 10^?5, 1.2 × 10^?4, and 5 × 10^?4, respectively.     

基于HEVC的多长度DCT变换的VLSI设计

为了满足下一代视频压缩标准HEVC中定义的四种不同长度DCT变换的要求,提出了一种灵活的DCT变换的VLSI架构。从DCT系数矩阵分解算法推导出可用于不同长度的一维DCT变换的硬件架构,在保持数据吞吐量不变的情况下,能够支持4,8,16,32点等不同长度的DCT变换。采用130 nm工艺库综合后,得到电路的最高工作频率为131 MHz,能够支持HEVC标准的4 k(4 096×2 048)高清视频进行60帧每秒的编码处理。     

A Regenerative Prescaled Clock Recovery for High-Bit-Rate OTDM Systems

A regenerative prescaled clock recovery device based on an optoelectronic version of the Miller divider has been tested in high-bit-rate OTDM systems. Tests at 4 × 2.5 and 4 × 10 Gbit/s have been performed to characterize the locking range and the frequency response of the device. The timing jitter of the recovered signal in the case of the 4 × 10 Gbit/s OTDM system does not exceed 0.5 ps. Finally, a comparison of two bit-error-rate measurements (with and without the clock recovery system) were carried out for the 4 × 10 Gbit/s OTDM system. The relevant penalty for each channel is negligible, while the maximum received power difference among the four channels at a bit error rate value of 10 ^− 10 is around 0.7 dB.     

All-digital thermal distribution measurement on field programmable gate array using ring oscillators

In this paper, a digital method for transient temperature distribution measurement of field programmable gate array (FPGA)-based systems is proposed. The smart thermal sensors used rely on correspondence between the delay and temperature in a ring oscillator. The tested temperature was converted into a time signal with a thermally-sensitive width. The output frequency is read out by a counter with a scan path, and then, transited to PC by a Universal Serial Bus (USB) interface. We capture the infrared images of the FPGA chip by infrared camera. The images were compared with the thermal map of the die constructed using an array of sensors. The tested temperature error varies by less than 1.6 °C in the range from 20 °C to 90 °C, and the maximum sampling rate is 330 Hz.